Design on ESD protection scheme for IC with power-down-mode operation

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 8, 2004, Pages 1378-1382

  Ker, Ming Dou ^a   Lin, Kun Hsien ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Electrostatic discharge (ESD); ESD bus; ESD protection scheme; Leakage current; Power down mode

Indexed keywords

DIODES; ELECTRIC DISCHARGES; ELECTRIC POTENTIAL; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; PORTABLE EQUIPMENT; ROBUSTNESS (CONTROL SYSTEMS); SPECTRUM ANALYSIS; TRIGGER CIRCUITS; VOLTAGE MEASUREMENT;

ELECTROSTATIC DISCHARGE BUS; ELECTROSTATIC DISCHARGES(ESD); ELECTROSTATIC PROTECTION SCHEME; POWER-DOWN MODES;

INTEGRATED CIRCUITS;

EID: 3843062359     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.831501     Document Type: Article

References (13)

1. S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, "A 1-V high-speed MTCMOS circuit scheme for power-down application circuits," IEEE J. Solid-Slate Circuits, vol. 32, pp. 861-869, June 1997.
2. S. Dabral and T. Maloney, Basic ESD and I/O Design. New York: Wiley, 1998.
3. Electrostatic Discharge Sensitivity Testing - Human Body Model (HBM) - Component Level, ESD Association Standard, Test Method ESD STM5.1, 1998.
4. C. Duvvury, R. Rountree, and O. Adams, "Internal chip ESD phenomena beyond the protection circuit," IEEE Trans. Electron Devices, vol. 35, pp. 2133-2139, Dec. 1988.
5. C. Johnson, T. J. Maloney, and S. Qawami, "Two unusual HBM ESD failure mechanisms on a mature CMOS process," in Proc. EOS/ESD Symp., 1993, pp. 225-231.
6. V. Puvvada and C. Duvvury, "A simulation study of HBM failure in an internal clock buffer and the design issue for efficient power pin protection strategy," in Proc. EOS/ESD Symp., 1998, pp. 104-110.
7. M.-D. Ker, "Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI," IEEE Trans. Electron Devices, vol. 46, pp. 173-183, Jan. 1999.
8. E. R. Worley, R. Gupta, B. Jones, R. Kjar, C. Nguyen, and M. Tennyson, "Sub-micron chip ESD protection schemes which avoid avalanching junctions," in Proc. EOS/ESD Symp., 1995, pp. 13-20.
9. J. M. Bessolo and G. Krieger, "ESD protection circuit and method for power-down application," U.S. Patent 5,229,635, July 20, 1993.
10. J. Lin, C. Duvvury, B. Haroun, I. Oguzman, and A. Somayaji, "A fail-safe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 μm CMOS I/O application," in IEDM Tech. Dig., 2002, pp. 349-352.
11. M. J. M. Pelgrom and E. C. Dijkmans, "A 3/5 V compatible I/O buffer," IEEE J. Solid-State Circuits, vol. 30, pp. 823-825, July 1995.
12. M.-D. Ker and K.-H. Lin, "ESD protection design for IC with powerdown-mode operation," in Proc. IEEE Int. Symp. Circuits and Systems, 2004, pp. 717-720.
13. M.-D. Ker, "Area-efficient VDD-to-VSS ESD clamp circuit by using substrate-triggering field-oxide device (STFOD) for whole-chip ESD protection," in Proc. Int. Symp. VLSI Technology, Systems, and Applications, 1997, pp. 69-73.