ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins

IEEE Transactions on Components and Packaging Technologies

Volumn 27, Issue 3, 2004, Pages 445-451

  Ker, Ming Dou ^a   Chang, Chyh Yih ^b   Chang, Yi Shu ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DISCHARGES; ELECTROSTATICS; EQUIVALENT CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MASKS; PHASE LOCKED LOOPS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DIODES; SPURIOUS SIGNAL NOISE;

ELECTROSTATIC DISCHARGE; ELECTROSTATIC DISCHARGE BUS; ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT; HUMAN BODY MODEL; VERTICAL SYNC SIGNAL;

CMOS INTEGRATED CIRCUITS;

EID: 4444266167     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAPT.2004.831762     Document Type: Article

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