Three-dimensional metal gate-high-Κ-GOI CMOSFETs on 1-poly-6-metal 0.18-μm Si devices

IEEE Electron Device Letters

Volumn 26, Issue 2, 2005, Pages 118-120

  Yu, D S ^a   Chin, Albert ^a,b   Liao, C C ^a   Lee, C F ^a   Cheng, C F ^a   Li, M F ^b   Yoo, Won Jong ^b   McAlister, S P ^c  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c NATIONAL RESEARCH COUNCIL CANADA   (Canada)

Author keywords

Ge on insulator (GOI); LaA1O3; Metal gate; MOSFET; Three dimensional (3 D)

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC FIELD EFFECTS; ELECTRON MOBILITY; HOLE MOBILITY; LANTHANUM COMPOUNDS; PERMITTIVITY; POLYSILICON; SEMICONDUCTING GERMANIUM; VLSI CIRCUITS;

CMOSFET; GERMANIUM-ON-INSULATOR (GOI); METAL GATE; POLYSILICON DEVICES;

MOSFET DEVICES;

EID: 13444301474     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.841861     Document Type: Article

References (14)

1. B.P. Shieh, L. C. Bassman, D.-K. Kim, K. C. Saraswat, M. D. Deal, J. P. McVittie, R. S. List, S. Nag, and L. Ting, "Integration and reliability issues for low capacitance air-gap interconnect structures," in Proc. IITC, 1998, pp. 125-127.
2. N. Yasutake, K. Ohuchi, M. Fujiwara, K. Adachi, A. Hokazono, K. Kojima, N. Aoki, H. Suto, T. Watanabe, T. Morooka, H. Mizuno, S. Magoshi, T. Shimizu, S. Mori, H. Oguma, T. Sasaki, M. Ohmura, K. Miyano, H. Yamada, H. Tomita, D. Matsushita, K. Muraoka, S. Inaba, M. Takayanagi, K. Ishimaru, and H. Ishiuchi, "A hp22 nm node low operating power (LOP) technology with subl0 nm gate length planar bulk CMOS devices," in Symp. VLSI Tech. Dig., 2004, pp. 84-85.
3. A.J. Walker, S. Nallamothu, E.-H. Chen, M. Mahajani, S. B. Herner, M. Clark, J. M. Cleeves, S. V. Dunton, V. L. Eckert, J. Gu, S. Hu, J. Knall, M. Konevecki, C. Petti, S. Radigan, U. Raghuram, J. Vienna, and M. A. Vyvoda, "3-D TFF-SONOS memory cell for ultra-high density file storage applications," in Symp. VSLI Tech. Dig., 2003, pp. 29-30.
4. M. Ohkura, K. Kusukawa, and H. Sunami, "Beam-induced seeded lateral epitaxy with suppressed impurity diffusion for a three-dimensional DRAM cell fabrication," IEEE Trans. Electron Devices, vol. 36, no. 3, pp. 333-339, Mar. 1989.
5. 2 for three-dimensional CMOS structures," IEEE Electron Device Lett., vol. 10, no. 3, pp. 144-146, Mar. 1989.
6. X. Lei, C. C. Liu, and S. Tiwari, "Multi-layers with buried structures (MLBS): An approach to three-dimensional integration," in Proc. IEEE SOI Conf., 2001, pp. 117-118.
7. 3 gate dielectrics," in Symp. VLSI Tech. Dig., 2003, pp. 119-120.
8. 3-Ge-on-Insulator MOSFETs," in IEDM Tech. Dig., 2003, pp. 319-322.
9. 2 n- and p-MOSFETs," IEEE Electron Device Lett., vol. 24, no. 11, pp. 739-741, Nov. 2003.
10. A. Khakifirooz and A. Antoniadis, "On the electron mobility in ultrathin SOI and GOI," IEEE Electron Device Lett., vol. 25, pp. 80-82, 2004.
11. T. Tezuka, S. Nakaharai, Y. Moriyama, N. Sugiyama, and S.-I. Takagi, "Selectively-formed high mobility SiGe-on-Insualtor p-MOSFETs with Ge-rich strained surface channels using local condensation technique," in Symp. VLSI Tech. Dig., 2004, pp. 198-199.
12. 3-Smart-Cut-Ge-on- Insulator nMOSFETs with high electron mobility," IEEE Electron Device Lett. vol. 25, no. 8, pp. 559-561, Aug. 2004.
13. 3-GOI nMOSFETs," in Proc. 62nd Device Research Conf., 2004, pp. 21-22.
14. T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, and S. Takagi, "(110)-surface strained-SOI CMOS devices with higher carrier mobility," in Symp. VLSI Tech. Dig., 2003, pp. 97-98.