Low temperature silicon circuit layering for three-dimensional integration

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 136-138

  Kim, S K ^a   Xue, L ^a   Tiwari, S ^a  

^a Cornell University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SILICON CIRCUIT LAYERING; SINGLE CRYSTAL SILICON; THREE DIMENSIONAL PARALLEL LAYERING PROCESS (3D-PLP); THREE-DIMENSIONAL INTEGRATION;

ADHESIVES; CONDUCTIVE PLASTICS; DIELECTRIC MATERIALS; DIGITAL CIRCUITS; DRY ETCHING; GRINDING (COMMINUTION); LOW TEMPERATURE ENGINEERING; SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY; SINGLE CRYSTALS; TRANSISTORS;

WSI CIRCUITS;

EID: 16244416502     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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