An efficient noise isolation technique for SOC application

IEEE Transactions on Electron Devices

Volumn 51, Issue 2, 2004, Pages 255-260

  Chen, Tung Sheng ^a   Lee, Chih Yuan ^a   Kao, Chin Hsing ^a  

^a NATIONAL DEFENSE UNIVERSITY   (Taiwan)

Author keywords

Integrated circuits (ICs); Pocket structure; Radio frequency (RF); Substrate noise

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; GATES (TRANSISTOR); NATURAL FREQUENCIES; SPURIOUS SIGNAL NOISE; SUBSTRATES;

NOISE ISOLATION TECHNIQUE; SYSTEM ON CHIP APPLICATION;

INTEGRATED CIRCUIT TESTING;

EID: 0442279706     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.821565     Document Type: Article

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