Leakage current variability in nanometer technologies

Proceedings - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005

Volumn 2005, Issue , 2005, Pages 60-63

  Anis, Mohab ^a   Aburahma, Mohamed H ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS; LEAKAGE CURRENTS; STATISTICAL METHODS;

DRAIN-INDUCED BARRIER LOWERING (DIBL); LEAKAGE REDUCTION TECHNIQUES; REVERSE BODY BIAS TECHNIQUE;

NANOTECHNOLOGY;

EID: 33748886314     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWSOC.2005.78     Document Type: Conference Paper

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