Exact lower bound for the number of switches in series to implement a combinational logic cell

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn 2005, Issue , 2005, Pages 357-362

  Schneider, F R ^a   Ribas, R P ^a   Sapatnekar, S S ^b   Reis, A I ^a,b  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT PERFORMANCE; COMPLEMENTARY SERIES/PARALLEL (CSP); PASS TRANSISTOR LOGIC (PTL); SWITCH NETWORKS;

ELECTRIC CHARGE; ELECTRIC LOADS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC RESISTANCE; ELECTRIC SWITCHES; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; TRANSISTORS;

COMBINATORIAL CIRCUITS;

EID: 33748565956     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2005.51     Document Type: Conference Paper

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