Library-less synthesis for static CMOS combinational logic circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1997, Pages 658-662

  Gavrilov, S ^a   Glebov, A ^a   Pullela, S ^a   Moore, S C ^a   Dharchoudhury, A ^a   Panda, R ^a   Vijayan, G ^a   Blaauw, D T ^a  

^a RUSSIAN ACADEMY OF SCIENCES   (Russian Federation)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; ELECTRIC NETWORK SYNTHESIS; LOGIC GATES; OPTIMIZATION;

LIBRARY MAPPING PHASE; LOGIC MINIMIZATION; TRANSISTOR LEVEL TECHNIQUES;

COMPUTER AIDED LOGIC DESIGN;

EID: 0031342379     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.1997.643608     Document Type: Conference Paper

References (12)