Technology mapping for high-performance static CMOS and pass transistor logic designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 5, 2001, Pages 577-589

  Jiang, Yanbin ^b,c   Sapatnekar, Sachin S ^a,d   Bamji, Cyrus ^b,e  

^a IEEE   (United States)

^b Iowa State University   (United States)

^c CADENCE DESIGN SYSTEMS   (United States)

^d University of Minnesota   (United States)

^e Canesta Inc   (United States)

Author keywords

Physical design; Technology mapping

Indexed keywords

PASS TRANSISTOR LOGIC DESIGNS;

INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; OPTIMIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 0035472377     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.953492     Document Type: Article

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