Mixed. PTL/static logic synthesis using genetic algorithms for low-power applications

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2002-January, Issue , 2002, Pages 458-463

  Cho, Geun Rae ^a   Chen, T ^a  

^a Department of Mechanical Engineering   (United States)

Author keywords

Application software; Boolean functions; Circuit synthesis; CMOS logic circuits; CMOS process; Data structures; Energy consumption; Genetic algorithms; Logic functions; Very large scale integration

Indexed keywords

ALGORITHMS; APPLICATION PROGRAMS; BOOLEAN FUNCTIONS; CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); DATA STRUCTURES; DELAY CIRCUITS; ELECTRIC POWER UTILIZATION; ENERGY UTILIZATION; GENETIC ALGORITHMS; LOGIC CIRCUITS; SYNTHESIS (CHEMICAL); VLSI CIRCUITS;

BENCHMARK CIRCUIT; CIRCUIT SYNTHESIS; CMOS LOGIC CIRCUITS; CMOS PROCESSS; LOGIC FUNCTIONS; LOW POWER APPLICATION; PASS-TRANSISTOR LOGIC; POWER DELAY PRODUCT;

LOGIC SYNTHESIS;

EID: 80053207944     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2002.996788     Document Type: Conference Paper

References (20)

1. S. Yamashita, K. Yano, and et. al, "Pass-Transistor/CMOS Collaborated Logic: The Best of Both Worlds," in Symposium on VLSI Circuits Digest of Technical Papers, pp. 31-32, 1997.
2. C. Yang and M. Ciesielski, "Synthesis For Mixed CMOS/PTL Logic : Preliminary Results," in International Workshop on Logic Synthesis, (Lake Tahoe, CA), 1999.
3. Y. Jiang, S. S. Sapatneker, and C. Bamji, "Technology Mapping for High Performance Static CMOS and Pass Transistor Logic Designs," in Technical Report, Dept of ECE, Iowa State University, 1999.
4. G. R. Cho and T. Chen, "On Mixed PTL/Static Logic for Low-Power and High-Speed Circuits," VLSI Design : An International Journal of Custom-Chip Design, Simulation, and Testing, vol. 12, no. 3, pp. 399-406, 2001.
5. F. Mailhot and G. D. Micheli, "Algorithms for Technology Mapping Based on Binary Decision Diagrams and Boolean Operations," IEEE Trans. on Computer-Aided Design of Integrated Circuit and Systems, vol. 12, pp. 599-620, May 1993.
6. K. Yano, Y. Sasaki, K. Rikino, , and K. Seki, "Top-Down Pass-Transistor Logic Design," IEEE Journal of Solid-State Circuits, vol. 31, pp. 792-803, June 1996.
7. M. Munteanu, P. A. Ivey, L. Seed, M. Psilogeorgopoulos, N. Powell, and I. Bogdan, "Single Ended Pass-Transistor Logic," in VLSI: Systems on a Chip(Kluwer Academic Publisher), pp. 206-217, 1999.
8. R. L. Rudell, Logic Synthesis for VLSI Design. Ph.D. dissertation, University of California, Berkeley, CA 94720, 1989.
9. G. D. Micheli, Synthesis and Optimization of Digital Circuits. McGraw-Hill, Inc., 1994.
10. R. Drechsler and B. Becker, Binary Decision Diagrams: Theory and Implementation. Kluwer Academic Publishers, 1998.
11. S. B. Akers, "Binary Decision Diagrams," IEEE Trans. on Computers, vol. C-27, pp. 509-516, June 1978.
12. R. E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. on Computers, vol. C-35, pp. 677-691, Aug. 1986.
13. D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning. Addison-Wesley, 1989.
14. Z. Michalewicz, Genetic Algorithms + Data Structure = Evolution Programs. Springer-Verlag, 1996.
15. S. Yang, Logic Synthesis and Optimization Benchmarks User Guide (Ver. 3.0). Triangle Park, NC:Microelectronics Center of North Carolina Research, 1991.
16. F. Somenzi, CUDD:CU Decision Diagram Package (Release 2.1.3). Dept. of ECE, University of Colorado at Boulder, Aug. 1997.
17. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, SIS: A System for Sequential Circuit Synthesis. Memorandum No. UCB/ERL M92/41, University of California, Berkeley, CA 94720, 1992.
18. Powermill and Pathmill User Guide. Synopsys, 2000.
19. R. Burch, F. N. Najam, P. Yang, and T. N. Trick, "A Monte Carlo Approach for Power Estimation," IEEE Trans. on Computer-Aided Design of Integrated Circuit and Systems, vol. 1, pp. 63-71, Mar. 1993.
20. F. N. Najm, "A survey of Power Estimation Techniques in VLSI Circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuit and Systems, vol. 2, pp. 446-455, Dec. 1994.