Transistor-level optimization of digital designs with flex cells

Computer

Volumn 38, Issue 2, 2005, Pages 53-61

  Roy, Rob ^a   Bhattacharya, Debashis ^a   Boppana, Vamsi ^a  

^a Zenasis Technologies Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; LOGIC CIRCUITS; LOGIC DESIGN; OPTIMIZATION; TRANSISTORS;

BINARY DECISION DIAGRAMS; CELL LAYOUT SYNTHESIS; FLEX CELLS; INTEGRATED CIRCUIT DESIGN;

DIGITAL INTEGRATED CIRCUITS;

EID: 15044339296     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.2005.74     Document Type: Article

References (14)

1. D. Chinnery and K. Keutzer, Closing the Gap between ASIC & Custom, Kluwer Academic Publishers, 2002.
2. Collett International, "1999 IC/ASIC Functional & Timing Verification Study," 1999; www.Collett.com.
3. R.B. Hitchcock, "Timing Verification and Timing Analysis Program," Proc. 19th Design Automation Conf., IEEE CS Press, 1982, pp. 594-604.
4. J.L. Burns and J.A. Feldman, "CSM-A Control-Logic Layout Synthesis System for High-Performance Microprocessors," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 1, 1998, pp. 14-23.
5. University of California, Berkeley, SIS Abstract Page; www.eecs.berkeley.edu/IPRO/Software/Catalog/Description/sis1.2.html.
6. M.R.C.M. Berkelaar and J.A.G. Jess, "Technology Mapping for Standard-Cell Generators," Proc. Int'l Conf. Computer-Aided Design, IEEE CS Press, 1988, pp. 470-473.
7. K. Taki, "A Survey for Pass-Transistor Logic Technologies - Recent Research and Developments and Future Prospects," Proc. Asia-South Pacific Design Automation Conf., IEEE CS Press, 1998, pp. 223-226.
8. R.E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. Computing, Aug. 1986, pp. 677-691.
9. C.P. Liu and J.A. Abraham, "Transistor-Level Synthesis for Static Combinational Circuits," Proc. 9th Great Lakes Symp. VLSI, IEEE CS Press, 1999, pp. 172-175.
10. M. Cirit and P. Hurat, "Automated Cell Optimization," Numerical Technologies white paper, 2002; www.synopsys.com/products/ntimrg/abstracts /AutomatedCellOptimization.html.
11. A. Reis et al., "The Library Free Technology Mapping Problem," Proc. Int'l Workshop Logic Synthesis, 1997, IEEE CS Press, pp. 102-106.
12. S. Bodapati and F.N. Najm, "Prelayout Estimation of Individual Wire Lengths," IEEE Trans. VLSI Systems, vol. 9, no. 6, 2001, pp. 943-958.
13. N. Sherwani, Algorithms for VLSI Physical Design Automation, 2nd ed., Kluwer Academic Publishers, 1995.
14. M. Johnson, D. Somasekhar, and K. Roy, "Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS," Proc. 36th Design Automation Conf., ACM Press, 1999, pp. 442-445.