Multilevel logic synthesis using hybrid pass logic and CMOS topologies

IEE Proceedings: Circuits, Devices and Systems

Volumn 150, Issue 5, 2003, Pages 445-452

  Yip, K ^a   Al Khalili, D ^b  

^a SYNOPSYS INC   (United States)

^b ROYAL MILITARY COLLEGE OF CANADA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; LOGIC CIRCUITS; MOSFET DEVICES; MULTIPLEXING EQUIPMENT; THRESHOLD VOLTAGE;

DESIGN ANALYZER; HYBRID PASS LOGIC; LOGIC SYNTHESIS; MULTILEVEL MAPPING ALGORITHM;

LOGIC DESIGN;

EID: 0348207754     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20030407     Document Type: Article

References (14)

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