Synthesis of single/dual-rail mixed PTL/static logic for low-power applications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 2, 2004, Pages 229-242

  Cho, Geun Rae ^a   Chen, Tom ^a  

^a Department of Mechanical Engineering   (United States)

Author keywords

Digital CMOS; Low power design; Technology mapping; Very large scale integration (VLSI)

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DYNAMIC PROGRAMMING; GENETIC ALGORITHMS; LOGIC DESIGN; LOGIC GATES; SILICON ON INSULATOR TECHNOLOGY; VLSI CIRCUITS;

BINARY DECISION DIAGRAMS; DIRECTED ACYCLIC GRAPH; LEVEL-RESTORING CIRCUIT; PASS-TRANSISTOR LOGIC SYNTHESIS;

INTEGRATED CIRCUIT LAYOUT;

EID: 1242263448     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.822121     Document Type: Article

References (28)

1. S. Yamashita et al., "Pass-transistor/CMOS collaborated logic: The best of both worlds," in Proc. Symp. VLSI Circuits Dig. Tech. Papers, 1997, pp. 31-32.
2. C. Yang and M. Ciesielski, "Synthesis for mixed CMOS/PTL logic: Preliminary results," in Int. Workshop Logic Synthesis, Lake Tahoe, CA, 1999.
3. Y. Jiang, S. S. Sapatneker, and C. Bamji, "Technology mapping for high performance static CMOS and pass transistor logic designs," IEEE Trans. VLSI Syst., vol. 9, pp. 577-589, Oct. 2001.
4. G. R. Cho and T. Chen, "On mixed PTL/static logic for low-power and high-speed circuits," VLSI Design: Int. J. Custom-Chip Design, Simulation, Testing, vol. 12, no. 3, pp. 399-406, 2001.
5. R. Zimmerman and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, pp. 1079-1090, July 1997.
6. K. Yano, Y. Sasaki, K. Rikino, and K. Seki, "Top-down pass-transistor logic design," IEEE J. Solid-State Circuits, vol. 31, pp. 792-803, June 1996.
7. M. Munteanu, P. A. Ivey, L. Seed, M. Psilogeorgopoulos, N. Powell, and I. Bogdan, "Single ended pass-transistor logic," in VLSI: Systems on a Chip. Norwell, MA: Kluwer, 1999, pp. 206-217.
8. T. Sakurai, "Alpha-power law MOSFET models and its applications to CMOS inverter delay and other formulas," IEEE J. Solid-State Circuits, vol. 25, pp. 584-594, Apr. 1990.
9. International Roadmap for Semiconductors, 2001.
10. A. Bellaouar and M. I. Elmasry, Low-Power Digital VLSI Design: Circuits and Systems. Norwell, MA: Kluwer, 1996.
11. R. L. Rudell, "Logic synthesis for VLSI design," Ph.D. dissertation, Univ. California, Berkeley, CA 94 720, 1989.
12. G. D. Micheli, Synthesis and Optimization of Digital Circuits. New York: McGraw-Hill, 1994.
13. F. Mailhot and G. D. Micheli, "Sequential circuit design using synthesis and optimization," in Proc. Eur. Design Automation Conf., 1990.
14. ____, "Algorithms for technology mapping based on binary decision diagrams and Boolean operations," IEEE Trans. Computer-Aided Design, vol. 12, pp. 599-620, May 1993.
15. L. Benni and G. D. Micheli, "A survey of Boolean matching techniques for library binding," ACM Trans. Design Automation Electron. Syst., vol. 2, pp. 193-226, 1997.
16. M. Zhao and S. S. Sapatneker, "A new structural pattern matching algorithm for technology mapping," in Proc. 38th ACM/IEEE Design Automation Conference, Las Vegas, NV, 2001.
17. R. Drechsler and B. Becker, Binary Decision Diagrams: Theory and Implementation. Norwell, MA: Kluwer, 1998.
18. S. B. Akers, "Binary decision diagrams," IEEE Trans. Comput., vol. C-27, pp. 509-516, June 1978.
19. R. E. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Trans. Comput., vol. C-35, pp. 677-691, Aug. 1986.
20. C. Meinel and T. Theobald, Algorithms and Data Structures in VLSI Design: OBDD-Foundations and Applications. Berlin, Germany: Springer-Verlag, 1998.
21. Y. Kukimoto, R. K. Brayton, and P. Sawkar, "Delay-optimal technology mapping by DAG covering," in Proc. Design Automation Conf., San Francisco, CA, 1998, pp. 348-351.
22. D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning. Reading, MA: Addison-Wesley, 1989.
23. Z. Michalewicz, Genetic Algorithms + Data Structure = Evolution Programs. Berlin, Germany: Springer-Verlag, 1996.
24. R. L. Haupt and S. E. Haupt, Practical Genetic Algorithms. New York: Wiley, 1998.
25. F. Somenzi, CUDD:CU Decision Diagram Package (Release 2.1.3). Boulder: Dept. Elect. Comput. Eng., Univ. Colorado, Aug. 1997.
26. Powermill and Pathmill User Guide, 2000.
27. C. Chuang et al., "Design considerations of scaled sub-0.1 μm PD/SOI CMOS circuits," Proc. ISQED, pp. 153-158, 2003.
28. G. R. Cho and T. Chen, "On the impact of fanout optimization and redundant buffer removal for mixed PTL synthesis," in IEEE/ACM 11th Int. Workshop Logic Synthesis, New Orleans, LA, 2002.