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Volumn 2005, Issue , 2005, Pages 946-953

UltraScan: Using Time-Division Demultiplexing/Multiplexing (TDDM/TDM) with VirtualScan for test cost reduction

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; DATA COMPRESSION; DEMULTIPLEXING; VIRTUAL REALITY;

EID: 33748511971     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1584060     Document Type: Conference Paper
Times cited : (13)

References (20)
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  • 4
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    • Built-in Test for Circuits with Scan Based Reseeding of Multiple Polynomial Linear Feedback Shift Registers
    • Feb
    • Hellebrand, J. Rajski, S. Tamick, S. Venkataraman, and B. Courtois, "Built-in Test for Circuits with Scan Based Reseeding of Multiple Polynomial Linear Feedback Shift Registers," IEEE Trans. on Computers, vol. C-44, No. 2, pp. 223-233, Feb. 1995.
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  • 5
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    • Test Data Decompression for Multiple Scan Designs with Boundary Scan
    • Nov
    • J. Rajski, J. Tyszer, and N. Zacharia, "Test Data Decompression for Multiple Scan Designs with Boundary Scan," IEEE Trans. on Computers, vol. 47, No. 11, pp. 1188-1200, Nov. 1998.
    • (1998) IEEE Trans. on Computers , vol.47 , Issue.11 , pp. 1188-1200
    • Rajski, J.1    Tyszer, J.2    Zacharia, N.3
  • 6
    • 0033740888 scopus 로고    scopus 로고
    • Virtual Scan Chains: A Means for Reducing Scan Length in Cores
    • A. Jas, B. Pouya, and N. Touba, "Virtual Scan Chains: A Means for Reducing Scan Length in Cores," Proc. VLSI TestSymp., pp. 73-78, 2000.
    • (2000) Proc. VLSI TestSymp , pp. 73-78
    • Jas, A.1    Pouya, B.2    Touba, N.3
  • 7
    • 0034848095 scopus 로고    scopus 로고
    • Test Volume and Application Time Reduction through Scan Chain Concealment
    • I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction through Scan Chain Concealment," Proc. Design Automation Conf., pp. 151-155, 2001.
    • (2001) Proc. Design Automation Conf , pp. 151-155
    • Bayraktaroglu, I.1    Orailoglu, A.2
  • 11
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    • X-Tolerant Compression and Application of Scan-ATPG Patterns in a BIST Architecture
    • P. Wohl, J. Waicukauski, S. Patel, and M. Amin, "X-Tolerant Compression and Application of Scan-ATPG Patterns in a BIST Architecture," Proc. Int 'I Test Conf., pp. 727-736, 2003.
    • (2003) Proc. Int 'I Test Conf , pp. 727-736
    • Wohl, P.1    Waicukauski, J.2    Patel, S.3    Amin, M.4
  • 12
    • 0033326167 scopus 로고    scopus 로고
    • Broadcasting Test Patterns to Multiple Circuits
    • Dec
    • K.-J. Lee, J. Chen, and C. Huang, "Broadcasting Test Patterns to Multiple Circuits," IEEE Trans. on Computer-Aided Design, vol. 18, No. 12, pp. 1793-1802, Dec. 1999.
    • (1999) IEEE Trans. on Computer-Aided Design , vol.18 , Issue.12 , pp. 1793-1802
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  • 13
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    • Reducing Test Application Time for Full Scan Embedded Cores
    • I. Hamzaoglu, and J.H. Patel, "Reducing Test Application Time for Full Scan Embedded Cores," Proc. Fault Tolerant Computing Symp., pp. 260-267, 1999.
    • (1999) Proc. Fault Tolerant Computing Symp , pp. 260-267
    • Hamzaoglu, I.1    Patel, J.H.2
  • 14
    • 0035687712 scopus 로고    scopus 로고
    • A Case Study on the Implementation of the Illinois Scan Architecture
    • F. Hsu, K. Butler, and J. Patel, "A Case Study on the Implementation of the Illinois Scan Architecture," Proc. Int'l Test Conf., pp. 538-547, 2001.
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  • 17
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    • Method and Apparatus for Broadcasting Scan Patterns in a Scan-Based Integrated Circuit,
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    • (2003)
    • Wang, L.-T.1    Wang, H.-P.2    Wen, X.3    Lin, M.-C.4    Lin, S.-H.5    Yeh, D.-C.6    Tsai, S.-W.7    Abdel-Hafez, K.S.8
  • 18
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    • Method and Apparatus for Shifting At-Speed Scan Patterns in a Scan-Based Integrated Circuit,
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.