At-speed logic BIST for IP cores

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 860-861

  Cheon, B ^a   Lee, E ^b   Wang, L T ^c   Wen, X ^c   Hsu, P ^b   Cho, J ^b   Park, J ^b   Chao, H ^b   Wu, S ^b  

^a SAMSUNG Electronics   (South Korea)

^b SYNTEST TECHNOLOGIES INC   (United States)

^c KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC BIST SCHEME; LOW-SPEED SE SIGNAL; MULTI-CLOCK DESIGNS; TEST POINT INSERTION;

LOGIC DEVICES; NATURAL FREQUENCIES; SIGNAL PROCESSING;

BUILT-IN SELF TEST;

EID: 33646911085     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.70     Document Type: Conference Paper

References (1)

1. L.-T. Wang, P. Hsu, S. Kao, M. Lin, H. Wang, H. Chao, X. Wen, "A Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Self-Test or Scan-Test," US Patent Application, 20020120896, August 29,2002.