VirtualScan: A new compressed scan technology for test cost reduction

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 916-925

  Wang, Laung Terng ^a   Wen, Xiaoqing ^b   Furukawa, Hiroshi ^c   Hsu, Fei Sheng ^a   Lin, Shyh Horng ^a   Tsai, Sen Wei ^a   Abdel Hafez, Khader S ^a   Wu, Shianling ^a  

^a SYNTEST TECHNOLOGIES INC   (United States)

^b NEC IC Microcomputer Systems Ltd   (Japan)

^c KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; COMPARATOR CIRCUITS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; REAL TIME SYSTEMS; SEQUENTIAL CIRCUITS;

AUTOMATIC TEST PATTERN GENERATION (ATPG); COMPRESSED SCAN TECHNOLOGY; DEEP SUB-MICRON (DSM) PROCESSES; ELECTRONIC DESIGN AUTOMATION (EDA);

INTEGRATED CIRCUIT TESTING;

EID: 18144386600     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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