Modeling and measurement of simultaneous switching noise coupling through signal via transition

IEEE Transactions on Advanced Packaging

Volumn 29, Issue 3, 2006, Pages 548-559

  Park, Jongbae ^a   Kim, Hyungsu ^a,b   Jeong, Youchul ^a   Kim, Jingook ^a   Pak, Jun So ^a,c   Kam, Dong Gun ^a   Kim, Joungho ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

^c NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

Noise coupling; Power ground noise; Printed circuit board (PCB); Reference plane change; Simultaneous switching noise (SSN); System on package (SoP); Via

Indexed keywords

BIT ERROR RATE; ELECTRIC LINES; JITTER; MULTILAYERS; PRINTED CIRCUIT BOARDS; SWITCHING SYSTEMS;

NOISE COUPLING; PSEUDORANDOM BIT SEQUENCE; REFERENCE PLANE CHANGE; SIMULTANEOUS SWITCHING NOISE; SYSTEM-ON-PACKAGE; TRANSMISSION LINE MATRIX METHOD;

ELECTRONICS PACKAGING;

EID: 33747610416     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2006.872996     Document Type: Article

References (28)

1. C. M. Scanlan and N. Karim, "System-in-package technology, application and trends," in Technology Paper, Techonline. Chandler, AZ: Amkor Technology, Inc., Jul. 2002.
2. R. R. Tummala, M. Swaminathan, M. M. Tentzeris, J. Laskar, G.-K. Chang, S. Sitaraman, D. Keezer, D. Guidotti, Z. Huang, K. Lim, L. Wan, S. K. Bhattacharya, V. Sundaram, F. Liu, and P. Markondeya Raj, "The SoP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade," IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 250-267, May 2004.
3. T. Sudo, H. Sasaki, N. Masuda, and J. L. Drewmak, "Electromagnetic interference (EMI) of system-on-package (SoP)," IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 304-314, May 2004.
4. J. Choi, S. Chun, N. Na, M. Swaminathan, and L. Smith, "A Methodology for the placement and optimization of decoupling capacitors for Gigahertz systems," in 13th Int. Conf. VLSI Design, Jan. 2000, pp. 156-161.
5. L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy, "Power distribution system design methodology and capacitor selection for modern CMOS technology," IEEE Trans. Adv. Packag., vol. 22, no. 3, pp. 284-291, Aug. 1999.
6. J. Lee, A. W. La, W. Fan, L. L. Wai, and J. Kim, "Effect of decoupling capacitor on signal integrity in applications with reference plane change," in Proc. Elec. Compon. Technol. Conf., May 2003, pp. 1283-1288.
7. M. Xu, T. H. Hubing, J. Chen, T. P. Van Doren, J. L. Drewnial, and R. E. DuBroff, "Power-bus decoupling with embedded capacitance in printed circuit board design," IEEE Trans. Electromagn. Compat., vol. 45, no. 1, pp. 22-30, Feb. 2003.
8. H. Kim and J. Kim, "Suppression of GHz range power/ground inductive impedance and simultaneous switching noise by using embedded film capacitor in multi-layer package and PCB," IEEE Wireless Compon. Lett., vol. 14, no. 2, pp. 71-73, Feb. 2004.
9. J. Kim, H. Kim, and J. Kim, "Efficient on-chip decoupling capacitor design on an 8-bit microcontroller to reduce simultaneous switching noise and electromagnetic radiated emission," IEICE Trans. Commun., vol. E86-B, no. 6, pp. 2077-2080, Jun. 2003.
10. Y. Jeong, A. C. W. Lu, L. L. Wai, W. Fan, and J. Kim, "Analysis of noise suppression techniques using embedded capacitor on split power bus in multi-layer package," in IEEE Int. Symp. Electromagn. Compat., Aug. 2004, pp. 215-220.
11. M. Swaminathan, J. Kim, I. Novak, and J. P. Libous, "Power distribution networks for system-on-package: Status and challenges," IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 286-300, May 2004.
12. J. Lee, M. D. Rotaru, M. K. Iyer, H. Kim, and J. Kim, "Analysis and suppression of SSN noise coupling between power/ground plane cavities through cutouts in multilayer packages and PCBs," IEEE Trans. Adv. Packag., vol. 28, no. 2, pp. 298-309, May 2005.
13. T. Okoshi, Planar Circuits for Microwaves and Lightwaves. Munich, Germany: Springer-Verlag, 1984.
14. J. Lee and J. Kim, "Efficiency of differential signaling on cavity noise suppression in application with reference plane change," in IEEE Int. Symp. Electromagn. Compat., Aug. 2004, pp. 203-208.
15. Microelectronics Packaging Handbook, pt. Part I, Chapman & Hall, New York, 1997. R. R. Tummala, E. J. Rymaszewski and A. G. Klopfenstein.
16. Y. Chen, Z. Wu, Y. Liu, and J. Fang, "Equivalent circuit models of via interactions in electronics packaging," in IEEE Int. Symp. Electromagn. Compat., Aug. 1994, pp. 377-380.
17. J. Fang, Y. Chen, Z. Wu, and D. Xue, "Model of interaction between signal vias and metal planes in electronics packaging," Elec. Performance Electron. Packag., pp. 211-214, Nov. 1994.
18. Y. Chen, Z. Chen, Z. Wu, D. Xue, and J. Fang, "A new approach to signal integrity analysis of high-speed packaging," Elec. Performance Electron. Packag., pp. 235-238, Oct. 1995.
19. J. Kim, M. D. Rotaru, J. Lee, J. Park, P. Alexander, M. K. Iyer, and J. Kim, "Analytical coupling model of SSN on power/ground planes to signal traces in high-speed multi-layer packages or boards," in Proc. IEEE 5th Electron. Packag. Technol. Conf., Singapore, Dec. 2003, pp. 45-50.
20. C. Wei, Y. Xiaoning, B. Archambeault, D. White, L. Min, and J. L. Drewniak, "EMI resulting from signal via transitions through the DC power bus," in Proc. IEEE Int. Symp. Electromagn. Compat., Aug. 2000, pp. 821-826.
21. J.-N. Hwang and T.-L. Wu, "Coupling of the ground bounce noise to the signal trace with via transition in partitioned power bus of PCB," in Proc. IEEE Int. Symp. Electromagn. Compat., Aug. 2002, pp. 733-736.
22. Z. Pantic-Tanner, E. Salgado, and F. Gisin, "Cross coupling between power and signal traces on printed circuit boards," in Proc. IEEE Int. Symp. Electromagn. Compat., Aug. 1998, pp. 624-628.
23. W. J. R. Hoefer, "The Transmission-line matrix method-Theory and applications," IEEE Trans. Microw. Theory Tech., vol. MTT-33, no. 10, pp. 882-893, Oct. 1985.
24. J. S. Pak and J. Kim, "3 GHz through-hole signal via model considering power/ground plane resonance coupling and via neck effect," in Proc. Elec. Compon. Technol. Conf., May 2003, pp. 1017-1023.
25. J. S. Pak, J. Lee, H. Kim, and J. Kim, "Prediction and verification of power/ground plane edge radiation excited by through-hole signal via based on balanced TLM and via coupling model," Elec. Performance Electron. Packag., pp. 27-29, Oct. 2003.
26. K. Lee and A. Barber, "Modeling and analysis of multichip module power supply planes," IEEE Trans. Compon., Packag., Manuf. Technol. B, vol. 18, no. 4, pp. 628-639, Nov. 1995.
27. D. M. Pozar, Microwave Engineering, 2nd ed. New York: Wiley, 1998, ch. Chapter 2.
28. J. S. Pak and J. Kim, "PCB power/ground plane edge radiation excited by high-frequency clock," in IEEE Int. Symp. Electromagn. Compat., Aug. 2004, pp. 9-13.