3GHz through-hole signal via model considering power/ground plane resonance coupling and via neck effect

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2003, Pages 1017-1022

  Pak, Jun So ^a   Kim, Joungho ^a  

^a Dept Elec Eng and Comp Sci   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; EQUIVALENT CIRCUITS; FREQUENCIES; OPTIMIZATION; PERMITTIVITY; PRINTED CIRCUIT BOARDS; SCATTERING PARAMETERS; SIGNAL DISTORTION;

EQUIVALENT CIRCUIT MODEL; GROUND PLANE RESONANCE COUPLING; NEAR FIELD PROBE MEASUREMENT; S-PARAMETER MEASUREMENT; VIA NECK EFFECT;

PRINTED CIRCUIT DESIGN;

EID: 0038688972     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Jin-Ho Kim, et al, "Analysis of Via in Multilayer Printed Circuit Boards for High-Speed Digital Systems," 3rd International Symposium on Electronic Materials and Packagings 2001, Jeju, Korea, Nov. 19-22. 2001.
2. Qizheng Gu, Y. Eric Yang, st al, "Modeling and Analysis of Vias in Multilayered Integrated Circuits," IEEE Trans-MTT, Vol. 41, No. 2, Feb. 1993, pp.206-214.
3. Ryosuke Ito, et al, "RF modeling of vertical interconnection between power-ground plane combined with 2D TLM," Electrical Performance of Electronic Packaging, 2001, Oct. 2001, pp. 339-342.
4. Kwunmyung Lee, Alan Barber, "Modeling and Analysis of Multichip Modeule Power Supply Planes," IEEE Trans-CPMT-B Vol. 18, No. 4, Nov. 1995, pp.628-639.