Low-power high-performance NAND match line content addressable memories

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 8, 2006, Pages 895-905

  Chaudhary, Vikas ^b,c   Clark, Lawrence T ^a,b  

^a IEEE   (United States)

^b Arizona State University   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Cache tag; Content addressable memory (CAM); Domino power; NAND match line

Indexed keywords

CACHE TAG; CONTENT ADDRESSABLE MEMORY (CAM); DOMINO POWER; NAND MATCH LINE;

BENCHMARKING; COMPUTER SIMULATION; NAND CIRCUITS; NETWORK PROTOCOLS; VLSI CIRCUITS;

ASSOCIATIVE STORAGE;

EID: 33747446265     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.878476     Document Type: Article

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