A low-power 2.5-GHz 90-nm level 1 cache and memory management unit

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 5, 2005, Pages 1190-1199

  Haigh, Jonathan R ^a   Wilkerson, Michael W ^a   Miller, Jay B ^a   Beatty, Timothy S ^a   Strazdus, Stephen J ^a   Clark, Lawrence T ^a,b  

^a INTEL CORPORATION   (United States)

^b Arizona State University   (United States)

Author keywords

Cache memories; Computer architecture; High speed integrated circuits; Low power; Microprocessors

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DATA REDUCTION; DECODING; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); STATIC RANDOM ACCESS STORAGE;

CONTENT-ADDRESSABLE MEMORY (CAM); HIGH-SPEED INTEGRATED CIRCUITS; LOW-POWER; MEMORY MANAGEMENT UNIT (MMU);

BUFFER STORAGE;

EID: 18444419119     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.845971     Document Type: Article

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