0.2-μm, 1.8-V, SOI, 550-MHz, 64-b PowerPC microprocessor with copper interconnects

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 11, 1999, Pages 1430-1435

  Aipperspach, Anthony G ^a   Allen, David H ^a,b,c,d   Cox, Dennis T ^a   Phan, Nghia V ^a   Storino, Salvatore N ^a  

^a IBM   (United States)

^b INTEL CORPORATION   (United States)

^c VTC Inc   (United States)

^d MICRON TECHNOLOGY INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COPPER; CRITICAL PATH ANALYSIS; ELECTRIC CURRENTS; HEATING; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE;

MEMORY INTEGRATED CIRCUITS;

MICROPROCESSOR CHIPS;

EID: 0033221866     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.799846     Document Type: Article

References (4)

1. S. N. Storino, S. R. Kunkel, R. J. Eickemeyer, and J. M. Borkenhagen, "A commercial multi-threaded RISC processor," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1998, pp. 236-237.
2. N. J. Rohrer, C. C. Akrout, M. G. Canada, D. Cawthron, B. Davari, R. Floyd, S. F. Geissler, R. D. Goldblatt, R. M. Houle, P. D. Kartschoke, D. Kramer, P. McCormick, G. M. Salem, L. Su, R. Schulz, and L. Whitney, "A 480 M Hz RISC microprocessor in a 0.12 μm Leff CMOS technology with copper interconnects," in ISSCC Dig. Tech. Papers, Feb. 1998, pp. 240-241.
3. F. Assaderaghi, W. Rausch, A. Ajmera, E. Leobandung, D. Schepis, L. Wagner, H.-J. Wann, R. Bolam, D. Yee, B. Davari, and G. Shahidi, "A 7.9/5.5 ps room/low temperature SOI CMOS," in Proc. IEDM '97, pp. 415-418.
4. G. Shahidi, A. Ajmera, F. Assaderaghi, R. J. Bolam, E. Leobandung, W. Rausch, D. Sankus, D. Schepis, L. F. Wagner, K. Wu, and B. Davari, "Partially-depleted SOI technology for digital logic," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1999, pp. 427-427.