-
2
-
-
0030413562
-
-
1996, p. 465.
-
C. Contiero, P. Galbiati, M. Palmieri, and L. Vecchi, "Characteristics and applications of a 0.6 ftm BipolarCMOSDMOS technology combining VLSI nonvolatile memories," in IEDM Tech. Dig., 1996, p. 465.
-
"Characteristics and Applications of a 0.6 Ftm BipolarCMOSDMOS Technology Combining VLSI Nonvolatile Memories," in IEDM Tech. Dig.
-
-
Contiero, C.1
Galbiati, P.2
Palmieri, M.3
Vecchi, L.4
-
4
-
-
84886448041
-
-
1997, p. 371.
-
R. Versari, A. Pieracci, S. Manzini, C. Contiero, and B. Riccö, "Hotcarrier reliability in submicrometer LDMOS transistors," IEDM Tech. Dig., 1997, p. 371.
-
"Hotcarrier Reliability in Submicrometer LDMOS Transistors," IEDM Tech. Dig.
-
-
Versari, R.1
Pieracci, A.2
Manzini, S.3
Contiero, C.4
Riccö, B.5
-
5
-
-
0024121747
-
-
vol. 35, p. 2210, Dec. 1988.
-
M. L. Chen, C. W. Leung, W. T. Cochran, W. Jungling, C. Dziuba, and T. Yang, "Suppression of hotcarrier effects in submicrometer CMOS technology," IEEE Trans. Electron Devices, vol. 35, p. 2210, Dec. 1988.
-
"Suppression of Hotcarrier Effects in Submicrometer CMOS Technology," IEEE Trans. Electron Devices
-
-
Chen, M.L.1
Leung, C.W.2
Cochran, W.T.3
Jungling, W.4
Dziuba, C.5
Yang, T.6
-
6
-
-
33747177392
-
-
96, p. 75.
-
C. Contiero, P. Galbiati, M. Palmieri, and L. Vecchi, "LDMOS implementation by large tilt implant in 0.6 ftm BCD," in Proc. IEEE ISPSD'96, p. 75.
-
"LDMOS Implementation by Large Tilt Implant in 0.6 Ftm BCD," in Proc. IEEE ISPSD'
-
-
Contiero, C.1
Galbiati, P.2
Palmieri, M.3
Vecchi, L.4
-
7
-
-
0022563701
-
-
7, p. 16, Jan. 1986.
-
T. Y. Chan, A. T. Wu, P. K. Ko, C. Hu, and R. R. Razouk, "Asymmetrical characteristics in LDD and minimum overlap MOSFET's," IEEE Electron Device Lett., vol. EDL7, p. 16, Jan. 1986.
-
"Asymmetrical Characteristics in LDD and Minimum Overlap MOSFET's," IEEE Electron Device Lett., Vol. EDL
-
-
Chan, T.Y.1
Wu, A.T.2
Ko, P.K.3
Hu, C.4
Razouk, R.R.5
-
8
-
-
0022026348
-
-
6, p. 135, Mar. 1985.
-
J. Hui, F. C. Hsu, and J. Moll, "A New substrate and gate current phenomenon in shortchannel LDD and minimum overlap devices," IEEE Electron Device Lett., vol. EDL6, p. 135, Mar. 1985.
-
"A New Substrate and Gate Current Phenomenon in Shortchannel LDD and Minimum Overlap Devices," IEEE Electron Device Lett., Vol. EDL
-
-
Hui, J.1
Hsu, F.C.2
Moll, J.3
-
9
-
-
0020208332
-
-
29, p. 1740, Nov. 1982.
-
S. Tarn, P. K. Ko, C. Hu, and R. S. Muller, "Correlation between substrate and gate currents in MOSFET's," IEEE Trans. Electron Devices, vol. ED29, p. 1740, Nov. 1982.
-
"Correlation between Substrate and Gate Currents in MOSFET's," IEEE Trans. Electron Devices, Vol. ED
-
-
Tarn, S.1
Ko, P.K.2
Hu, C.3
Muller, R.S.4
-
10
-
-
0030190768
-
-
vol. 39, p. 1079, 1996.
-
C. Jungemann, R. Thoma, and W. L. Engl, "A soft threshold lucky electron model for efficient and accurate numerical device simulation" Solid State Electron., vol. 39, p. 1079, 1996.
-
"A Soft Threshold Lucky Electron Model for Efficient and Accurate Numerical Device Simulation" Solid State Electron.
-
-
Jungemann, C.1
Thoma, R.2
Engl, W.L.3
-
11
-
-
0031103504
-
-
vol. 44, p. 472, Mar. 1997.
-
C. Tsai, D. E. Burk, and K. D. T. Ngo, "Physical modeling of the power VDMOST for computeraided design of integrated circuit," IEEE Trans. Electron Devices, vol. 44, p. 472, Mar. 1997.
-
"Physical Modeling of the Power VDMOST for Computeraided Design of Integrated Circuit," IEEE Trans. Electron Devices
-
-
Tsai, C.1
Burk, D.E.2
Ngo, K.D.T.3
-
12
-
-
0030415670
-
-
1996, p. 485.
-
A. Pieracci, M. Lanzoni, C. Contiero, S. Manzini, P. Galbiati, and B. Riccö, "Extraction of channel doping profile in DMOS transistors," IEDM Tech. Dig., 1996, p. 485.
-
"Extraction of Channel Doping Profile in DMOS Transistors," IEDM Tech. Dig.
-
-
Pieracci, A.1
Lanzoni, M.2
Contiero, C.3
Manzini, S.4
Galbiati, P.5
Riccö, B.6
-
13
-
-
0025401607
-
-
vol. 37, p. 797, Mar. 1990.
-
Y. S. Kirn and J. G. Possum, "Physical DMOST modeling for highvoltage 1C CAD," IEEE Trans. Electron Devices, vol. 37, p. 797, Mar. 1990.
-
"Physical DMOST Modeling for Highvoltage 1C CAD," IEEE Trans. Electron Devices
-
-
Kirn, Y.S.1
Possum, J.G.2
-
15
-
-
0024611790
-
-
vol. 36, p. 375, Feb. 1989.
-
M. K. Orlowski, C. Werner, and J. P. Klink, "Model for the electric fields in LDD MOSFET'sPart I: Field peaks on the source side," IEEE Trans. Electron Devices, vol. 36, p. 375, Feb. 1989.
-
"Model for the Electric Fields in LDD MOSFET'sPart I: Field Peaks on the Source Side," IEEE Trans. Electron Devices
-
-
Orlowski, M.K.1
Werner, C.2
Klink, J.P.3
-
16
-
-
0024610729
-
-
vol. 36, p. 382, Feb. 1989.
-
M. K. Orlowski and C. Werner, "Model for the electric fields in LDD MOSFET'sPart II: Field distribution on the drain side," IEEE Trans. Electron Devices, vol. 36, p. 382, Feb. 1989.
-
"Model for the Electric Fields in LDD MOSFET'sPart II: Field Distribution on the Drain Side," IEEE Trans. Electron Devices
-
-
Orlowski, M.K.1
Werner, C.2
-
17
-
-
3643120618
-
-
8, p. 480, Oct. 1987.
-
R. Izawa and E. Takeda, "The impact of JVdrain length and gatedrain/source overlap on submicrometer LDD devices for VLSI," IEEE Electron Device Lett., vol. EDL8, p. 480, Oct. 1987.
-
"The Impact of JVdrain Length and Gatedrain/source Overlap on Submicrometer LDD Devices for VLSI," IEEE Electron Device Lett., Vol. EDL
-
-
Izawa, R.1
Takeda, E.2
-
18
-
-
0022880171
-
-
T. Hamamoto, Y. Oowaki, K. Hieda, and K. Ohuchi, "Asymmetry of the substrate current characteristics enhanced by the gate bird's beak," in 1986 Symp. VLSI Technol., p. 67.
-
"Asymmetry of the Substrate Current Characteristics Enhanced by the Gate Bird's Beak," in 1986 Symp. VLSI Technol., P. 67.
-
-
Hamamoto, T.1
Oowaki, Y.2
Hieda, K.3
Ohuchi, K.4
-
19
-
-
0021640334
-
-
1984, p. 774.
-
H. Katto, K. Okuyama, S. Meguro, R. Nagai, and S. Ikeda, "Hotcarrier degradation modes and optimization of LDD MOSFETS," IEDM Tech. Dig., 1984, p. 774.
-
"Hotcarrier Degradation Modes and Optimization of LDD MOSFETS," IEDM Tech. Dig.
-
-
Katto, H.1
Okuyama, K.2
Meguro, S.3
Nagai, R.4
Ikeda, S.5
-
20
-
-
0030101999
-
-
vol. 39, p. 419, 1996.
-
A. O. Conde, F. J. G. Sanchez, and J. J. Liou, "An improved method for extracting the difference between drain and source resistances in MOSFETs" Solid State Electron., vol. 39, p. 419, 1996.
-
"An Improved Method for Extracting the Difference between Drain and Source Resistances in MOSFETs" Solid State Electron.
-
-
Conde, A.O.1
Sanchez, F.J.G.2
Liou, J.J.3
|