Physical modeling of the power VDMOST for computer-aided design of integrated circuit

IEEE Transactions on Electron Devices

Volumn 44, Issue 3, 1997, Pages 472-480

  Tsai, Chin Yu ^a   Burk, Dorothea E ^a   Ngo, Khai D T ^a  

^a University of Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MODELS; POWER ELECTRONICS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; VOLTAGE MEASUREMENT;

CAPACITANCE VOLTAGE CHARACTERISTICS; PARAMETER EXTRACTION; POWER INTEGRATED CIRCUIT DESIGN; VERTICAL DOUBLE DIFFUSED MOS TRANSISTOR;

MOSFET DEVICES;

EID: 0031103504     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.556158     Document Type: Article

References (19)

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