The LOTTERYBUS on-chip communication architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 6, 2006, Pages 596-608

  Lahiri, Kanishka ^a,b   Raghunathan, Anand ^a,b   Lakshminarayana, Ganesh ^c  

^a IEEE   (United States)

^b NEC LABORATORIES AMERICA   (United States)

^c Alphion Corp   (United States)

Author keywords

Bus architecture; On chip communication; Randomized arbitration; System on Chip (SoC)

Indexed keywords

BUS ARCHITECTURE; ON-CHIP COMMUNICATION; RANDOMIZED ARBITRATION; SYSTEM-ON-CHIP (SOC);

AUTOMATIC TELLER MACHINES; BANDWIDTH; FREQUENCY ALLOCATION; HARDWARE; MICROPROCESSOR CHIPS; PROBABILISTIC LOGICS; TELECOMMUNICATION TRAFFIC; TIME DIVISION MULTIPLE ACCESS;

COMMUNICATION SYSTEMS;

EID: 33746887787     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.878210     Document Type: Article

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