Tiny tera: A packet switch core

IEEE Micro

Volumn 17, Issue 1, 1997, Pages 26-33

  McKeown, Nick ^a,c,d,h   Izzard, Martin ^b,e,f,g   Mekkittikul, Adisak ^a,h,i   Ellersick, William ^a,j,k,l   Horowitz, Mark ^a,m,n  

^a STANFORD UNIVERSITY   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c HEWLETT PACKARD LABORATORIES   (United Kingdom)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e UNIVERSITY OF KWAZULU NATAL   (South Africa)

^f UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^g TRINITY COLLEGE   (United Kingdom)

^h Stanford University   (United States)

ⁱ WICHITA STATE UNIVERSITY   (United States)

^j ERICSSON RESEARCH   (United States)

^k M/A COM   (United States)

^l RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^m Electrical Engineering Department

ⁿ RAMBUS INC   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; CONGESTION CONTROL (COMMUNICATION); CROSSBAR EQUIPMENT; PACKET SWITCHING; PHASE CONTROL; QUEUEING THEORY; SCHEDULING; TELECOMMUNICATION LINKS; TELECOMMUNICATION TRAFFIC;

CHIP TO CHIP SERIAL LINKS; CLOCK DISTRIBUTION; HEAD OF LINE BLOCKING; MULTICAST TRAFFIC; PACKET SWITCH; SCHEDULER; UNICAST TRAFFIC; VIRTUAL OUTPUT QUEUEING;

SWITCHES;

EID: 0030871480     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.566194     Document Type: Article

References (11)

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