-
4
-
-
84859967419
-
SPIN: A scalable, packet switched, on-chip micro-network
-
A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, and C. A. Zeferino, "SPIN: A Scalable, Packet Switched, On-Chip Micro-Network," in Proc. Design Automation & Test Europe (DATE) Conf., pp. 70-73, 2003.
-
(2003)
Proc. Design Automation & Test Europe (DATE) Conf.
, pp. 70-73
-
-
Adriahantenaina, A.1
Charlery, H.2
Greiner, A.3
Mortiez, L.4
Zeferino, C.A.5
-
5
-
-
4444343175
-
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory
-
June
-
S. Han, A. Baghdadi, M. Bonaciu, S. Chae, and A. A. Jerraya, "An Efficient Scalable and Flexible Data Transfer Architecture for Multiprocessor SoC with Massive Distributed Memory," in Proc. Design Automation Conf., pp. 250-255, June 2004.
-
(2004)
Proc. Design Automation Conf.
, pp. 250-255
-
-
Han, S.1
Baghdadi, A.2
Bonaciu, M.3
Chae, S.4
Jerraya, A.A.5
-
6
-
-
0034428335
-
DS-CDMA wired bus with simple interconnection topology for parallel processing system LSIs
-
R. Yoshimura, K. T. Boon, T. Ogawa, S. Hatanaka, T. Matsuoka, and K. Taniguchi, "DS-CDMA Wired Bus With Simple Interconnection Topology for Parallel Processing System LSIs," in Proc: Int. Solid-State Circuits Conf., pp. 370-371, 2000.
-
(2000)
Proc: Int. Solid-State Circuits Conf.
, pp. 370-371
-
-
Yoshimura, R.1
Boon, K.T.2
Ogawa, T.3
Hatanaka, S.4
Matsuoka, T.5
Taniguchi, K.6
-
7
-
-
2542430318
-
Design of high-performance system-on-chips using communication architecture tuners
-
K.Lahiri, A.Raghunathan, and S.Dey, "Design of High-Performance System-on-Chips Using Communication Architecture Tuners," IEEE Trans. on CAD, vol. 23, no. 6, pp. 919-932, 2004.
-
(2004)
IEEE Trans. on CAD
, vol.23
, Issue.6
, pp. 919-932
-
-
Lahiri, K.1
Raghunathan, A.2
Dey, S.3
-
8
-
-
0042635838
-
A tool for describing and evaluating hierarchical real-time bus scheduling policies
-
June
-
T. Meyerowitz, C. Pinello, and A. Sangiovanni-Vincentelli, "A Tool for Describing and Evaluating Hierarchical Real-Time Bus Scheduling Policies," in Proc. Design Automation Conf., pp. 312-317, June 2003.
-
(2003)
Proc. Design Automation Conf.
, pp. 312-317
-
-
Meyerowitz, T.1
Pinello, C.2
Sangiovanni-Vincentelli, A.3
-
9
-
-
4444324957
-
DyAD - Smart routing for networks-on-chip
-
June
-
J. Hu and R. Marculescu, "DyAD - Smart Routing For Networks-on-Chip," in Proc. Design Automation Conf., pp. 260-263, June 2004.
-
(2004)
Proc. Design Automation Conf.
, pp. 260-263
-
-
Hu, J.1
Marculescu, R.2
-
10
-
-
0036045512
-
Constraint-driven communication synthesis
-
June
-
A. Pinto, L. P. Carloni, and A. Sangiovanni-Vincentelli, "Constraint-Driven Communication Synthesis," in Proc. Design Automation Conf., pp. 783-788, June 2002.
-
(2002)
Proc. Design Automation Conf.
, pp. 783-788
-
-
Pinto, A.1
Carloni, L.P.2
Sangiovanni-Vincentelli, A.3
-
13
-
-
0032674656
-
Policy optimization for dynamic power management
-
June
-
L.Benini, A.Bogliolo, G.Paleologo, and G.D.Micheli, "Policy Optimization for Dynamic Power Management," IEEE Trans. on CAD, vol. 18, pp. 813-833, June 1999.
-
(1999)
IEEE Trans. on CAD
, vol.18
, pp. 813-833
-
-
Benini, L.1
Bogliolo, A.2
Paleologo, G.3
Micheli, G.D.4
-
14
-
-
77953845567
-
Adaptive disk spin-down policies for mobile computers
-
Apr.
-
F. Douglis, P. Krishnan, and B. Bershad, "Adaptive Disk Spin-Down Policies for Mobile Computers," in USENIX Symp. Mobile and Location Independent Computing, pp. 121-137, Apr. 1995.
-
(1995)
USENIX Symp. Mobile and Location Independent Computing
, pp. 121-137
-
-
Douglis, F.1
Krishnan, P.2
Bershad, B.3
-
18
-
-
84861286399
-
-
"CB-12." http://www.necel.com/cbic/en/cb12/cb12.html.
-
CB-12
-
-
-
19
-
-
0003479594
-
-
Addison-Wesley, Menlo Park, CA
-
H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, Menlo Park, CA, 1990
-
(1990)
Circuits, Interconnections, and Packaging for VLSI
-
-
Bakoglu, H.B.1
-
20
-
-
84861275203
-
-
Design Compiler 2003.12, Synopsys Inc.
-
"Design Compiler 2003.12, Synopsys Inc.," http://www.synopsys. com/ products/logic/design_compiler.html.
-
-
-
|