Process for 20 nm T gate on Al0.25Ga0.75As/In 0.2Ga0.8As/GaAs epilayer using two-step lithography and zigzag foot

Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

Volumn 24, Issue 4, 2006, Pages 1869-1872

  Lee, K S ^a   Kim, Y S ^a   Lee, K T ^a   Jeong, Y H ^a  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON BEAM LITHOGRAPHY; ELECTRON SCATTERING; GATES (TRANSISTOR); LITHOGRAPHY; LOW TEMPERATURE PHENOMENA; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; POLYMETHYL METHACRYLATES; WSI CIRCUITS;

AS/GAAS EPILAYER; HIGHER-VOLTAGE ELECTRON BEAM; NANOMETER STRUCTURES; T-GATE;

SEMICONDUCTING GALLIUM ARSENIDE;

EID: 33746480334     PISSN: 10711023     EISSN: None     Source Type: Journal    
DOI: 10.1116/1.2218871     Document Type: Article

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