A low-cost parallel scalable FPGA architecture for regular and irregular LDPC decoding

IEEE Transactions on Communications

Volumn 54, Issue 7, 2006, Pages 1215-1223

  Verdier, François ^a   Declercq, David ^a  

^a UNIVERSITÉ DE CERGY PONTOISE   (France)

Author keywords

Field programmable gate arrays (FPGAs); Hardware constrained low density parity check (LDPC) codes; Parallel implementation

Indexed keywords

CODES (SYMBOLS); CONSTRAINT THEORY; DECODING; ENCODING (SYMBOLS); MATHEMATICAL MODELS;

LOW-DENSITY PARITY-CHECK CODES; PARALLELIZATION; PSEUDORANDOMNESS CONSTRAINTS; SYSTEM-ON-CHIP PLATFORMS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33746328065     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCOMM.2006.877980     Document Type: Article

References (26)

1. R. Gallager, Low-Density Parity-Check Codes. Cambridge, MA: MIT Press, 1963.
2. D. MacKay, "Good error-correcting codes based on very sparse matrices," IEEE Trans. Inf. Theory, vol. 45, no. 2, pp. 399-431, Mar. 1999.
3. F. Kschischang, B. Frey, and H.-A. Loeliger, "Factor graphs and the sum product algorithm," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 498-519, Feb. 2001.
4. E. Eleftheriou and S. Ölçer, "Low-density parity-check codes for digital subscriber lines," in Proc. IEEE Int. Conf. Commun., Apr.-May 2002, vol. 3, pp. 1752-1757.
5. H. Song, R. Todd, and J. Cruz, "Performance of LDPC codes on magnetic recording channels," in Proc. Turbo-Codes Conf., Brest, France, 2000, pp. 395-398.
6. ETSI Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for broadcasting, interactive services, news gathering and other broadband satellite applications (DVB-S2), EN 302 307, ETSI, Apr. 2005.
7. C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error-correcting coding and decoding: Turbo codes," in Proc. IEEE Int. Conf. Commun., Geneva, Switzerland, 1993, pp. 1064-1070.
8. E. Yeo, B. Nikolić, and V. Anantharam, "Architectures and implementations of low-density parity-check decoding algorithms," in Proc. IEEE Int. Symp. Circuits Syst., Scottsdale, AZ, May 2002, vol. III, pp. 437-440.
9. E. Boutillon, J. Castura, and F. Kschischang, "Decoder-first code design," in Proc. Turbo Codes Conf., Brest, France, Sep. 2000, pp. 459-462.
10. V. Sorokine, F. Kschischang, and S. Pasupathy, "Gallager codes for CDMA applications - Part II: Implementations, complexity, and system capacity," IEEE Trans. Commun., vol. 48, no. 11, pp. 1818-1828, Nov. 2000.
11. T. Zhang and K. Parhi, "An FPGA implementation of (3,6)-regular low-density parity-check code decoder," EURASIP J. Appl. Signal Process., no. 6, pp. 530-542, May 2003.
12. A. J. Blanksby and C. J. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 404-412, Mar. 2002.
13. A. Selvarathinam, G. Choi, K. Narayanan, A. Prabhakar, and E. Kim, "A massively scaleable decoder architecture for low-density parity-check codes," in Proc. IEEE Int. Symp. Circuits Syst., Bangkok, Thailand, May 2003, vol. II, pp. 61-64.
14. S. Ölçcer, "Decoder architecture for array-code-based LDPC codes," in Proc. IEEE Global Commun. Conf., San Francisco, CA, Dec. 2003, pp. 2046-2050.
15. H. Zhong and T. Zhang, "Design of VLSI implementation-oriented LDPC codes," in Proc. IEEE Veh. Technol. Conf., Orlando, FL, Oct. 2003, pp. 670-673.
16. D. E. Hocevar, "LDPC code construction with flexible hardware implementation," in Proc. IEEE Int. Conf. Commun., Anchorage, AK, May 2003, pp. 2708-2712.
17. Y. Chen and D. Hocevar, "An FPGA and ASIC implementation of rate 1/2 8088-b irregular low density parity check decoder," in Proc. IEEE Global Commun. Conf., San Francisco, CA, Dec. 2003, pp. 113-117.
18. M. M. Mansour and N. R. Shanbhag, "A novel design methodology for high-performance programmable decoder cores for AA-LDPC codes," in Proc. IEEE Workshop Signal Process. Syst., 2003, pp. 29-34.
19. M. M. Mansour and N. R. Shanbhag, "High-thoughput LDPC decoders," IEEE Trans. VLSI Syst., vol. 11, no. 6, pp. 976-996, Dec. 2003.
20. J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, "Reduced-complexity decoding of LDPC codes," IEEE Trans. Commun., vol. 53, no. 8, pp. 1288-1299, Aug. 2005.
21. F. Verdier and D. Declercq, "An LDPC parity check matrix construction for parallel hardware decoding," in Proc. 3rd Int. Symp. Turbo Codes, Related Topics, Brest, France, Sep. 2003, pp. 235-238.
22. M. G. Luby, M. Mitzenmacher, M. A. Shokrollahi, and D. A. Spielman, Improved low-density parity-check codes using irregular graphs and belief propagation Digital Equipment Corp. Sys. Res. Center, Berkeley, CA, Tech. Rep. TR-97-044, 1997 [Online]. Available: urlciteseer.nj.nec.com/luby99improved.html
23. D. Declercq and F. Verdier, "Optimization of LDPC finite precision belief propagation decoding with discrete density evolution," in Proc. 3rd Int. Symp. Turbo Codes, Related Topics, Brest, France, Sep. 2003, pp. 479-482.
24. J. Zhang and M. Fossorier, "Shuffled belief propagation decoding," in Proc. Asilomar Conf., Pacific Grove, CA, Nov. 2002, pp. 8-15.
25. L. Ping and W. Leung, "Decoding low density parity check codes with finite quantization bits," IEEE Commun. Lett., vol. 4, no. 2, pp. 62-64, Feb. 2000.
26. T. Zhang, Z. Wang, and K. Parhi, "On finite precision implementation of low density parity check codes decoder," in Proc. IEEE Int. Conf. Circuits Syst., Sydney, Australia, May 2001, vol. 4, pp. 202-205.