A massively scaleable decoder architecture for low-density parity-check codes

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2003, Pages

  Selvarathinam, Anand ^a   Choi, Gwan ^a   Narayanan, Krishna ^a   Prabhakar, Abhiram ^a   Kim, Euncheol ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

BER FER; Hardware Scaling; LDPC Decoder; Parallel Architecture; VLSI

Indexed keywords

BIT ERROR RATE; CODES (SYMBOLS); COMPUTER HARDWARE; COMPUTER SIMULATION;

HARDWARE SCALING;

DECODING;

EID: 0038760887     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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