An FPGA implementation of (3,6)-regular low-density parity-check code decoder

Eurasip Journal on Applied Signal Processing

Volumn 2003, Issue 6, 2003, Pages 530-542

  Zhang, Tong ^a   Parhi, Keshab K ^b  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b University of Minnesota   (United States)

Author keywords

Decoder; Error correcting coding; FPGA; Low density parity check codes

Indexed keywords

COMPUTER HARDWARE; DECODING; ENCODING (SYMBOLS); ERROR CORRECTION;

LOW-DENSITY PARITY-CHECK CODES;

SIGNAL PROCESSING;

EID: 0038547114     PISSN: 11108657     EISSN: None     Source Type: Journal    
DOI: 10.1155/S1110865703212105     Document Type: Article

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