Noise figure optimization of inductively degenerated CMOS LNAs with integrated gate inductors

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 7, 2006, Pages 1409-1422

  Belostotski, Leonid ^a   Haslett, James W ^a  

^a UNIVERSITY OF CALGARY   (Canada)

Author keywords

CMOS; Gate inductor; Gate resistance; Low noise amplifier (LNA); Noise optimation; Parasitic resistance; RF

Indexed keywords

ELECTRIC INDUCTORS; GATES (TRANSISTOR); OPTIMIZATION; RADIO FREQUENCY AMPLIFIERS; SPURIOUS SIGNAL NOISE;

LOW-NOISE AMPLIFIERS (LNAS); ON-CHIP GATE INDUCTORS; PARASITIC RESISTANCES; POWER MATCHED TECHNIQUES;

CMOS INTEGRATED CIRCUITS;

EID: 33746177011     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2006.875188     Document Type: Article

References (28)

1. D. Shaeffer and T. Lee, "A 1.5-V, 1.5-GHz CMOS low noise amplifier," IEEE J. Solid-State Circuits, vol. 32, no. 745-759, May 1997.
2. D. Shaeffer and T. Lee, "Corrections to 'A 1.5-V, 1.5-GHz CMOS low noise amplifier'," IEEE J. Solid-State Circuits, vol. 40, no. 6, p. 1397, Jun. 2005.
3. T.-K. Nguyen, C.-H. Kim, M.-S. Yang, and S.-G. Lee, "CMOS low-noise amplifier design optimization techniques," IEEE Trans. Microw. Theory Tech., vol. 52, no. 5, pp. 1433-1442, May 2004.
4. L. Franca-Neto, B. Bloechel, and K. Soumyanath, "17-GHz and 24-GHz LNA designs based on extended-s-parameter with microstrip-on-die in 0.18-μm logic CMOS technology," in Proc. 29th Eur. Solid-State Circuits Conf., Estoril, Portugal, Sep. 2003, pp. 149-152.
5. V. Aparin and L. Larson, "Modified derivative superposition method for linearizing FET low-noise amplifiers," IEEE Trans. Microw. Theory Tech., vol. 53, no. 2, pp. 571-581, Feb. 2005.
6. H.-W. Chiu, S.-S. Lu, and Y.-S. Lin, "A 2.17-dB NF 5-GHz-band monolithic CMOS LNA with 10-mW DC power consumption," IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 813-824, Mar. 2005.
7. P. Sivonen and A. Parssinen, "Analysis and optimization of packaged inductively degenerated common-source low-noise amplifiers with ESD protection," IEEE Trans. Microw. Theory Tech., vol. 53, no. 4, pp. 1304-1313, Apr. 2005.
8. Z. Li, R. Quintal, and K. O, "A dual-band CMOS front-end with two gain modes for wireless LAN applications," IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2069-2073, Nov. 2004.
9. T. Lee, The Design of CMOS Radio-Erequency Integrated Circuits, 2nd ed. New York: Cambridge Univeristy Press, 2004.
10. I. Aoki, S. Kee, D. Rutledge, and A. Hajimiri, "Distributed active transformer - A new power-combining and impedance-transformation technique," IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 316-331, Jan. 2002.
11. P. Andreani and H. Sjöland, "Noise optimization of an inductively degenerated CMOS low noise amplifier," IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process., vol. 48, no. 9, pp. 835-841, Sep. 2001.
12. F. Trofimenkoff, J. Haslett, and R. Smallwood, "Hot electron thermal noise models for FETs," Int. J. Electron., vol. 44, no. 3, pp. 257-272, Mar. 1978.
13. A. van der Ziel, "The state of solid state device noise research," in Proc. 4th Int. Conf. Physical Aspects Noise Solid-State Dev., Noordwijkerhout, Netherlands, May 1976, pp. 41-51.
14. A. van der Ziel, Noise in Solid State Devices and Circuits. New York: Wiley, 1986.
15. J. Haslett and F. Trofimenkoff, "Small-signal, high-frequency equivalent circuit for the metal-oxide-semiconductor field-effect transistor," Proc. Inst. Elect. Eng., vol. 116, no. 5, pp. 699-702, May 1969.
16. R. A. Pucel, H. Haus, and H. Statz, "Signal and noise properties of gallium arsenide microwave field-effect transistors," Adv. Electron. Electron. Phys., vol. 38, pp. 195-265, 1975.
17. J. Haslett and F. Trofimenkoff, "Thermal noise in field-effect devices," Proc. Inst. Elect. Eng., vol. 116, no. 11, pp. 1863-1868, Nov. 1969.
18. W. Liu, MOSFET Models for SPICE Simulation Including BSIM3v3 and BSIM4. New York: Wiley, 2001.
19. A. van der Ziel, "Thermal noise in FETs," in Proc. Inst. Radio Eng., 1962, vol. 50, pp. 1808-1812.
20. A. Scholten, H. J. Tromp, L. Tiemeijer, R. van Langevelde, R. Havens, P. de Vreede, R. Roes, P. Woerlee, A. Montree, and D. Klaassen, "Accurate thermal noise model for deep-submicron CMOS," in Proc. Int. Electron. Dev. Meeting, 1999, pp. 155-158.
21. A. Scholten, L. Tiemeijer, R. van Langevelde, R. Havens, A. Zegers-van Duijnhoven, and V. Venezia, "Noise modeling for RF CMOS circuit simulation," IEEE Trans. Electron. Dev., vol. 50, no. 3, pp. 618-632, Mar. 2003.
22. B. Razavi, R.-H. Yan, and K. Lee, "Impact of distributed gate resistance on the performance of MOS devices," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 41, no. 11, pp. 750-754, Nov. 1994.
23. K. Christensen, T. Lee, and E. Bruun, "A high dynamic range programmable CMOS front-end filter with a tuning range from 1850 to 2400 MHz," Analog Integr. Circuits Signal Process., vol. 42, no. 1, pp. 55-64, Jan. 2005.
24. G. Girlando and G. Palmisano, "Noise figure and impedance matching in RF cascode amplifiers," IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process., vol. 46, no. 11, pp. 1388-1396, Nov. 1999.
25. H. Halladay and A. van der Ziel, "On the high frequency excess noise and equivalent circuit representation of the MOS-FET with n-type channel," Solid-State Electron., vol. 12, no. 3, pp. 161-176, Mar. 1969.
26. H. A. Haus, W. R. Atkinson, W. H. Fonger, W. Mcleod, G. M. Branch, W. A. Harris, E. K. Stodola, W. B. Davenport Jr., S. Harrison, and T. Talpey, "Representation of noise in linear twoports," Proc. IRE, vol. 48, no. 1, pp. 66-74, Jan. 1960.
27. A. Youssef and J. Haslett, "Guidelines for the noise optimization of 0.18-μm CMOS tuned LNAs," in Proc. 2004 47th Midwest Symp. Circuits Syst., Hiroshima, Japan, Jul. 2004, pp. III-9-III-12.
28. D. Shaeffer, "The design and implementation of low-power CMOS radio receivers," Ph.D. dissertation, Stanford Univ., Stanford, CA, Dec. 1998.