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IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 48, Issue 9, 2001, Pages 835-841

Noise optimization of an inductively degenerated CMOS low noise amplifier

(2) Andreani, Pietro a,b Sjöland, Henrik a,b

a IEEE (Sweden)

b LUND UNIVERSITY (Sweden)

Author keywords

CMOS; Gate induced current noise; LNA; Noise; RF

Indexed keywords

GATE-INDUCED CURRENT NOISE; INDUCTIVE SOURCE DEGENERATION TOPOLOGY; LOW NOISE AMPLIFIER; QUASI-STATIC TRANSISTOR MODEL;

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC IMPEDANCE; EQUIVALENT CIRCUITS; MATHEMATICAL MODELS; MOSFET DEVICES; SPURIOUS SIGNAL NOISE; THERMAL NOISE; TRANSFER FUNCTIONS;

AMPLIFIERS (ELECTRONIC);

EID: 0035456082 PISSN: 10577130 EISSN: None Source Type: Journal
DOI: 10.1109/82.964996 Document Type: Article

Times cited : (237)

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