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Volumn 1, Issue , 2005, Pages 606-611

Process variation robust clock tree routing

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC CLOCKS; FORESTRY; INTELLIGENT SYSTEMS; MONTE CARLO METHODS;

EID: 33745940293     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120974     Document Type: Conference Paper
Times cited : (13)

References (18)
  • 2
    • 33747993282 scopus 로고
    • Zero-skew clock routing trees with minimum wirelength
    • September
    • K. D. Boese and A. B. Kahng. Zero-skew clock routing trees with minimum wirelength. In Proc. IEEE Int. ASIC Conf., pages 1.1.1-1.1.5, September 1992.
    • (1992) Proc. IEEE Int. ASIC Conf. , pp. 111-115
    • Boese, K.D.1    Kahng, A.B.2
  • 3
    • 33751393338 scopus 로고    scopus 로고
    • Statistical timing analysis considering spatial correlations using a single pert-like traversal
    • [31 H. Chang and S. Sapatnekar. Statistical timing analysis considering spatial correlations using a single pert-like traversal. In Proc. Design Automation Conf, 2003.
    • (2003) Proc. Design Automation Conf
    • Chang, H.1    Sapatnekar, S.2
  • 5
    • 0030697759 scopus 로고    scopus 로고
    • Optimal wire-sizing function with fringing capacitance consideration
    • Chung-Ping Chen and D. F Wong. Optimal wire-sizing function with fringing capacitance consideration. In Proc. Design Automation Conf, pages 604-407, 1997.
    • (1997) Proc. Design Automation Conf , pp. 604-407
    • Chen, C.-P.1    Wong, D.F.2
  • 10
    • 0027262847 scopus 로고
    • A clustering-based optimization algorithm in zero-skew routing
    • June
    • M. Edahiro. A clustering-based optimization algorithm in zero-skew routing. In Proc. Design Automation Conf, pages 612-616, June 1993.
    • (1993) Proc. Design Automation Conf , pp. 612-616
    • Edahiro, M.1
  • 12
  • 14
    • 0033719785 scopus 로고    scopus 로고
    • A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance
    • V. Mehrotra, S. Sam, D. Boning, A. Chandrakasan, R. Vallishayee, and S. Nassif. A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance. In Proc. Design Automation Conf, pages 172-175, 2000.
    • (2000) Proc. Design Automation Conf , pp. 172-175
    • Mehrotra, V.1    Sam, S.2    Boning, D.3    Chandrakasan, A.4    Vallishayee, R.5    Nassif, S.6
  • 16
    • 0036660080 scopus 로고    scopus 로고
    • UST/DME: A clock tree router for general skew constraints
    • C.-W. A. Tsao and C.-K. Koh. UST/DME: A clock tree router for general skew constraints. ACM (TODAES), 7:359-379, 2002.
    • (2002) ACM (TODAES) , vol.7 , pp. 359-379
    • Tsao, C.-W.A.1    Koh, C.-K.2
  • 17
    • 84888035000 scopus 로고    scopus 로고
    • A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty
    • May
    • D. Velenis, E. Friedman, and M. Papaefthymiou. A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. In Proc. IEEE Int. Symp. on Circuits and Systems, pages 4.422-4.425, May 2001.
    • (2001) Proc. IEEE Int. Symp. on Circuits and Systems , pp. 4422-4425
    • Velenis, D.1    Friedman, E.2    Papaefthymiou, M.3
  • 18
    • 0029722521 scopus 로고    scopus 로고
    • Useful-skew clock routing with gate sizing for low power design
    • J. G. Xi and W. W.-M. Dai. Useful-skew clock routing with gate sizing for low power design. In Proc. Design Automation Conf, pages 383-388, 1996.
    • (1996) Proc. Design Automation Conf , pp. 383-388
    • Xi, J.G.1    Dai, W.W.-M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.