A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 422-425

  Velenis, Dimitrios ^a   Friedman, Eby G ^a   Papaefthymiou, Marios C ^b  

^a University of Rochester   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; CRITICAL DATA; DELAY UNCERTAINTIES; ENVIRONMENTAL VARIATIONS; EXTRACTION ALGORITHMS; PROCESS PARAMETER VARIATIONS; SYNCHRONOUS CIRCUITS; SYNCHRONOUS SYSTEM;

CLOCK DISTRIBUTION NETWORKS; ELECTRIC CLOCKS; TOPOLOGY;

ALGORITHMS;

EID: 84888035000     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922263     Document Type: Conference Paper

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