Optimal wire-sizing function with fringing capacitance consideration

Proceedings - Design Automation Conference

Volumn , Issue , 1997, Pages 604-607

  Chen, Chung Ping ^a   Wong, D F ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DELAY CIRCUITS; ELECTRIC INSULATING MATERIALS; ELECTRIC RESISTANCE; VLSI CIRCUITS;

INTERCONNECTION DELAY; WIRE SIZING;

ELECTRIC WIRE;

EID: 0030697759     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/266021.266295     Document Type: Conference Paper

References (12)