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1
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0141608680
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Characterization of line-edge roughness in resist patterns and estimation of its effect on device performance
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A. Yamaguchi, R. Tsuchiya, H. Fukuda, O. Komuro, H. Kawada, and T. Iizumi, "Characterization of Line-Edge Roughness in Resist Patterns and Estimation of its Effect on Device Performance," Proc. SPIE 5038, 689-698 (2003).
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(2003)
Proc. SPIE
, vol.5038
, pp. 689-698
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Yamaguchi, A.1
Tsuchiya, R.2
Fukuda, H.3
Komuro, O.4
Kawada, H.5
Iizumi, T.6
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2
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0035364688
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An experimentally validated analytical model for gate Line-Edge Roughness (LER) effects on technology scaling
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C. Diaz, H.-J. Tao, Y.-C. Ku, A. Yen, and K. Young, "An Experimentally Validated Analytical Model for Gate Line-Edge Roughness (LER) Effects on Technology Scaling." IEEE Electron Device Letters, 22(6), 287-289 (2001).
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(2001)
IEEE Electron Device Letters
, vol.22
, Issue.6
, pp. 287-289
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Diaz, C.1
Tao, H.-J.2
Ku, Y.-C.3
Yen, A.4
Young, K.5
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3
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0034763365
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Experimental determination of the impact of poly silicon LER on sub-100 nm transistor performance
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K. Patterson, J. L. Sturtevant, J. Alvis, N. Benavides, D. Bonser, N. Cave, C. Nelson-Thomas, B. Taylor, K. Turnquest, "Experimental Determination of the Impact of Poly silicon LER on sub-100 nm Transistor Performance," Proc. SPIE 4344, 809-814 (2001).
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(2001)
Proc. SPIE
, vol.4344
, pp. 809-814
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Patterson, K.1
Sturtevant, J.L.2
Alvis, J.3
Benavides, N.4
Bonser, D.5
Cave, N.6
Nelson-Thomas, C.7
Taylor, B.8
Turnquest, K.9
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4
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0036029137
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Study of gate line edge roughness effects in 50 nm bulk MOSFET devices
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S. Xiong, J. Bokor, Q. Xiang, P. Fisher, I. Dudley, and P. Rao, "Study of Gate Line Edge Roughness Effects in 50 nm Bulk MOSFET Devices." Proc. SPIE 4689, 733-741 (2002).
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(2002)
Proc. SPIE
, vol.4689
, pp. 733-741
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Xiong, S.1
Bokor, J.2
Xiang, Q.3
Fisher, P.4
Dudley, I.5
Rao, P.6
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5
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0042532317
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Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness
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A. Asenov, S. Kaya, and A. R. Brown, "Intrinsic Parameter Fluctuations in Decananometer MOSFETs Introduced by Gate Line Edge Roughness," IEEE Trans. Electron. Devices 50(5), 1254-1260 (2003).
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(2003)
IEEE Trans. Electron. Devices
, vol.50
, Issue.5
, pp. 1254-1260
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Asenov, A.1
Kaya, S.2
Brown, A.R.3
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6
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0141608654
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Does line edge roughness matter?: FEOL and BEOL perspectives
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Q. Lin, C. Black, C. Detavernier, L. Gignac, K. Guarini, B. Herbst, H. Kim, P. Oldiges, K. Petrillo, and M. Sanchez, "Does Line Edge Roughness Matter?: FEOL and BEOL Perspectives," Proc. SPIE 5039, 1076-1085 (2003).
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(2003)
Proc. SPIE
, vol.5039
, pp. 1076-1085
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Lin, Q.1
Black, C.2
Detavernier, C.3
Gignac, L.4
Guarini, K.5
Herbst, B.6
Kim, H.7
Oldiges, P.8
Petrillo, K.9
Sanchez, M.10
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7
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4344603151
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Metrology of LER: Influence of line-edge roughness (LER) on transistor performance
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A. Yamaguchi, K. Ichinose, S. Shimamoto, H. Fukuda, R. Tsuchiya, K. Ohnishi, H. Kawada, and T. Iizumi, "Metrology of LER: influence of line-edge roughness (LER) on transistor performance," Proc. SPIE 5375, 468-476 (2004).
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(2004)
Proc. SPIE
, vol.5375
, pp. 468-476
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Yamaguchi, A.1
Ichinose, K.2
Shimamoto, S.3
Fukuda, H.4
Tsuchiya, R.5
Ohnishi, K.6
Kawada, H.7
Iizumi, T.8
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8
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3843130605
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Effect of line edge roughness (LER) and line width roughness (LWR) on sub-100 nm device performance
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J.-Y. Lee, J. Shin, H.-W. Kim, S.-G. Woo, H.-K. Cho, W.-S. Han, and J.-T. Moon, "Effect of line edge roughness (LER) and line width roughness (LWR) on Sub-100 nm Device Performance," Proc. SPIE 5376, 426-433 (2004).
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(2004)
Proc. SPIE
, vol.5376
, pp. 426-433
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Lee, J.-Y.1
Shin, J.2
Kim, H.-W.3
Woo, S.-G.4
Cho, H.-K.5
Han, W.-S.6
Moon, J.-T.7
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9
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4344658756
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Influence of line edge roughness on MOSFET devices with sub-50nm gates
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K. Shibata, N. Izumi, and K. Tsujita, "Influence of line edge roughness on MOSFET devices with sub-50nm gates," Proc. SPIE 5375, 865-873 (2004).
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(2004)
Proc. SPIE
, vol.5375
, pp. 865-873
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Shibata, K.1
Izumi, N.2
Tsujita, K.3
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11
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4944245120
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Line edge roughness and critical dimension variation: Fractal characterization and comparison using model functions
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V. Constantoudis, G.P. Patsis, L.H.A. Leunissen, and E. Gogolides, "Line edge roughness and critical dimension variation: Fractal characterization and comparison using model functions," J. Vac. Sci. Technol. B 22, 1974-1981 (2004).
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(2004)
J. Vac. Sci. Technol. B
, vol.22
, pp. 1974-1981
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Constantoudis, V.1
Patsis, G.P.2
Leunissen, L.H.A.3
Gogolides, E.4
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12
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33749681265
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(private communication) called this to my attention
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Daniel J. C. Herr (private communication) called this to my attention.
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Herr, D.J.C.1
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13
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4344674373
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Determination of optimal parameters for CD-SEM measurement of line edge roughness
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B. D. Bunday, M. Bishop, D. McCormack, J. S. Villarrubia, A. E. Vladár, R. Dixson, T. Vorburger, and N. G. Orji, "Determination of Optimal Parameters for CD-SEM Measurement of Line Edge Roughness," Proc. SPIE 5375, 515-533 (2004).
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(2004)
Proc. SPIE
, vol.5375
, pp. 515-533
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Bunday, B.D.1
Bishop, M.2
McCormack, D.3
Villarrubia, J.S.4
Vladár, A.E.5
Dixson, R.6
Vorburger, T.7
Orji, N.G.8
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14
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24644477476
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Unbiased estimation of linewidth roughness
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in press
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J. S. Villarrubia and B. D. Bunday, "Unbiased Estimation of Linewidth Roughness," Proc. SPIE 5752 (2005), in press.
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(2005)
Proc. SPIE
, vol.5752
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Villarrubia, J.S.1
Bunday, B.D.2
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15
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0004161838
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Cambridge University Press, Cambridge
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W. H. Press, B. P. Flannery, S. A. Teukolsky, and W. T. Vetterling, Numerical Recipes in C, (Cambridge University Press, Cambridge, 1988) p. 520.
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(1988)
Numerical Recipes in C
, pp. 520
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Press, W.H.1
Flannery, B.P.2
Teukolsky, S.A.3
Vetterling, W.T.4
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