Impact of Capacitor Dielectric Relaxation on a 14-bit 70-MS/s Pipeline ADC in 3-V BiCMOS

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 12, 2003, Pages 2077-2086

  Zanchi, Alfio ^a   Tsay, Frank ^a   Papantonopoulos, Ioannis ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

Analog to digital converters (ADCs); Dielectric relaxation; Pipelined architecture; Silicon germanium BiCMOS; Switched caDacitor circuits

Indexed keywords

ABSORPTION; ACOUSTIC NOISE; ALGORITHMS; AMPLIFICATION; CAPACITORS; CMOS INTEGRATED CIRCUITS; CODE DIVISION MULTIPLE ACCESS; COMPUTER SIMULATION; DIELECTRIC RELAXATION; HYSTERESIS; OPERATIONAL AMPLIFIERS; OPTIMIZATION; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SEMICONDUCTING GERMANIUM; SEMICONDUCTING SILICON;

DYNAMIC ELEMENT MATCHING (DEM); INTEGRAL NONLINEARITY (INL); PIPELINED ARCHITECTURE; SWITCHED-CAPACITOR CIRCUITS;

ANALOG TO DIGITAL CONVERSION;

EID: 0346972311     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.819168     Document Type: Conference Paper

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