A 21mW 8b 125MS/s ADC occupying 0.09mm 2 in 0.13μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Mulder, Jan ^a   Ward, Christopher M ^a   Lin, Chi Hung ^a   Kruse, Dave ^a   Westra, Jan R ^a   Lugthart, Marcel L ^a   Arslan, Erol ^a   Van De Plassche, Rudy J ^a   Bult, Klaas ^a   Van Der Goes, Frank M L ^a  

^a Broadcom Netherlands   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATORS; DIFFERENTIAL PAIRS; DIGITAL ENCODERS; OFFSET COMPENSATION SWITCHES;

CMOS INTEGRATED CIRCUITS; DIFFERENTIAL AMPLIFIERS; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; ELECTRIC SWITCHES; ERROR ANALYSIS; INTERPOLATION; SIGNAL TO NOISE RATIO; TOPOLOGY; TRANSFER FUNCTIONS;

ANALOG TO DIGITAL CONVERSION;

EID: 2442696345     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. B.P. Brandt and J. Lutsky, "A 75-mW, 10-b, 20-MSPS CMOS Subranging ADC with 9.5 Effective Bits at Nyquist," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1788-1795, Dec. 1999.
2. R.C. Taft and M.R. Tursi, "A 100-MS/s 8-b CMOS Subranging ADC with Sustained Parametric Performance from 3.8V down to 2.2," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 331-338, Mar. 2001.