8-Bit 150-MHz CMOS A/D converter

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 3, 2000, Pages 308-317

  Wang, Yun Ti ^a,b   Razavi, Behzad ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Silicon Bridge   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; INTERPOLATION; PIPELINE PROCESSING SYSTEMS; SIGNAL DISTORTION; SIGNAL TO NOISE RATIO; TIMING CIRCUITS;

SAMPLE-AND-HOLD CIRCUITS;

ANALOG TO DIGITAL CONVERSION;

EID: 0033897913     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.826812     Document Type: Article

References (6)

1. C. Lane, "A 10-Bit, 60-MS/s flash ADC," in Proc. BCTM, Sept. 1989, pp. 44-47.
2. H. Kimura et al., " A 10-b 300-MHz interpolated parallel A/D converter," IEEE J. Solid-State Circuits, vol. 28, pp. 438-146, Apr. 1993.
3. A. G. W. Venes and R. J. van de Plassche, "An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track- and-hold preprocessing," IEEE J. Solid-State Circuits, vol. 31. pp. 1846-1853, Dec. 1996.
4. W. Black and D. A. Hodges, "Time interleaved converter arrays," IEEE J. Solid-State Circuits, vol. SC-15, pp. 1022-1029, Dec. 1980.
5. Y. C. Jenq, "Digital spectra of nonuniformly sampled signals: Fundamentals and high-speed waveform digitizers," IEEE Trans. Instrum. Meas., vol. 37, pp. 245-251, June 1988.
6. B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press, 1995.