RF figures-of-merit for process optimization

IEEE Transactions on Electron Devices

Volumn 51, Issue 12, 2004, Pages 2121-2128

  Hurkx, G A M ^a   Agarwal, Prabhat ^a   Dekker, Ronald ^a   van der Heijden, E ^a   Veenstra, H ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Bipolar analog integrated circuits; Bipolar transistors; Optimization methods; Technology assessment

Indexed keywords

BIPOLAR TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; LINEAR NETWORK SYNTHESIS; OPTIMIZATION;

BIPOLAR ANALOG INTEGRATED CIRCUITS; PROCESS OPTIMIZATION; TECHNOLOGY ASSESSMENT;

BIPOLAR INTEGRATED CIRCUITS;

EID: 10644263642     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.838511     Document Type: Article

References (11)

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