A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 4, 2006, Pages 759-770

  Oh, Hwa Joon ^a,b   Mueller, Silvia M ^a,c,h   Jacobi, Christian ^c   Tran, Kevin D ^b   Cottier, Scott R ^a,b   Michael, Brad W ^b,g   Nishikawa, Hiroo ^d   Totsuka, Yonetaro ^e   Namatame, Tatsuya ^b,f   Yano, Naoka ^f   Machida, Takashi ^f   Dhong, Sang H ^a,b  

^a IEEE

^b IBM   (United States)

^c IBM   (Germany)

^d IBM JAPAN LTD   (Japan)

^e SONY CORPORATION   (Japan)

^f TOSHIBA CORPORATION   (Japan)

^g STI Design Center   (United States)

^h SAARLAND UNIVERSITY   (Germany)

Author keywords

Floating point arithmetic; Integrated circuit design; Microprocessors; Very large scale integration

Indexed keywords

FLOATING-POINT ARITHMETIC; INTEGRATED CIRCUIT DESIGN; MULTIMEDIA APPLICATIONS; VERY LARGE-SCALE INTEGRATION;

INTEGRATED CIRCUIT LAYOUT; MULTIMEDIA SYSTEMS; VLSI CIRCUITS;

MICROPROCESSOR CHIPS;

EID: 33645675534     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.870924     Document Type: Conference Paper

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