PowerPC 970 in 130nm and 90nm technologies

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Rohrer, Norman J ^a   Canada, Miles ^a   Cohen, Erwin ^a   Ringler, Mat ^a   Mayfield, Mike ^a   Sandon, Peter ^a   Kartschoke, Paul ^a   Heaslip, Jay ^a   Allen, James ^a   McCormick, Peter ^a   Pflüger, Thomas ^b   Zimmerman, Jeff ^a   Lichtenau, Cedric ^b   Werner, Tobias ^a   Salem, Gerard ^a   Ross, Mike ^a   Appenzeller, David ^a   Thygesen, Dana ^a  

^a IBM   (United States)

^b IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

GATE OXIDES; POWER SAVINGS; VOLTAGE SCALING;

COMPUTER ARCHITECTURE; DIODES; ELECTRIC CLOCKS; FORMAL LOGIC; LEAKAGE CURRENTS; OPTICAL INTERCONNECTS; OPTIMIZATION; SIGNAL ENCODING; SILICON ON INSULATOR TECHNOLOGY; STATIC RANDOM ACCESS STORAGE;

MICROPROCESSOR CHIPS;

EID: 2442663906     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. D.C. Bossen, et al., "Power4 System Design for High Reliability," IEEE Micro, vol. 22, no. 2, pp. 16-24, Mar. 2002.
2. P. Sandon,"PowerPC 970: First in a New Family of 64-bit High Performance PowerPC Processors," Microprocessor Forum, Oct. 2002.
3. F. Ferriaolo, "Synchronous Wave-Pipelined Interface," Hot Chips, Aug. 1999.
4. Cedric Lichtenau et al., "PowerTune: Advanced Frequency and Power Scaling on PowerPC 970+," ISSCC Dig. Tech. Papers, pp. 356-357, Feb. 2004.
5. E. Leobandung et al., "Scalability of SOI Technology into 0.13μm 1.2V CMOS Generation," IEEE Electron Devices Meeting Digest, pp. 403-406, 1998.
6. M. Khare et al., "A High Performance 90nm SOI Technology with 0.992mm 6T-SRAM Cell," IEEE Electron Devices Meeting Digest, pp. 407-410, Dec. 2002.