Aladin: A layout synthesys tool for analog integrated circuits

Analog Integrated Circuits and Signal Processing

Volumn 46, Issue 3, 2006, Pages 215-230

  Zhang, L ^a   Kleine, U ^b   Raut, R ^a   Jiang, Y ^c  

^a Gina Cody School of Engineering and Computer Science   (Canada)

^b OTTO VON GUERICKE UNIVERSITY   (Germany)

^c University of Nevada Las Vegas   (United States)

Author keywords

Analog integrated circuits; Layout synthesis; Module generation; Placement; Routing

Indexed keywords

COMPACTION; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; SIMULATED ANNEALING; TOOLS;

ANALOG INTEGRATED CIRCUITS; LAYOUT SYNTHESIS; MODULE GENERATION; PLACEMENT; ROUTING;

INTEGRATED CIRCUITS;

EID: 33644506767     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10470-006-1271-z     Document Type: Article

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