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Volumn 6, Issue , 1999, Pages

Reliability driven module generation for analog layouts

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRICAL CONSTRAINTS; VOLTAGE DROP;

EID: 0032629282     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article
Times cited : (9)

References (16)
  • 1
    • 0024647840 scopus 로고
    • ILAC: An automated layout tool for analog CMOS circuits
    • April
    • J. Rijmenants, et al., "ILAC: An Automated Layout Tool for Analog CMOS Circuits," IEEE J. Solid-state Circuits., Vol. 24, No. 2, pp. 417-425, April 1989.
    • (1989) IEEE J. Solid-state Circuits. , vol.24 , Issue.2 , pp. 417-425
    • Rijmenants, J.1
  • 2
    • 0026118974 scopus 로고
    • Koan/Anagram 11: New tools for devi'ce-level analog placement and routing
    • March
    • J. M. Cohn, et al., "KOAN/ANAGRAM 11: New Tools for Devi'ce-Level Analog Placement and Routing," IEEE J. Solid-State Circuits, Vol. 26, No. 3, pp. 330-342, March 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , Issue.3 , pp. 330-342
    • Cohn, J.M.1
  • 3
    • 0027559437 scopus 로고
    • ALSYN: Flexible rule-based layout synthesis for analog IC's
    • March
    • V. Mreyer zu Bexten, et al., "ALSYN: Flexible Rule-Based Layout Synthesis for Analog IC's," IEEE J. Solid-state Circuits, Vol. 28, No. 3, pp. 261-268, March 1993.
    • (1993) IEEE J. Solid-state Circuits , vol.28 , Issue.3 , pp. 261-268
    • Mreyer Zu Bexten, V.1
  • 4
    • 0025383839 scopus 로고
    • OPASYN: A compiler for CMOS operational amplifiers
    • Feb
    • H. Y. Koh, et al., "OPASYN: A Compiler for CMOS Operational Amplifiers," IEEE Trans. Computer-Aided Design, Vol. 9, No. 2, pp. 113-1'25, Feb. 1990.
    • (1990) IEEE Trans. Computer-Aided Design , vol.9 , Issue.2 , pp. 113-125
    • Koh, H.Y.1
  • 5
    • 0029342926 scopus 로고
    • An analogue module generator for mixed analogue/digital ASIC design
    • July-Aug
    • G. Gielen, et. al., "An Analogue Module Generator for Mixed Analogue/Digital ASIC Design," International Journal of Circuit Theory and Applications, Vol. 23, pp. 269-283, July-Aug. 1995.
    • (1995) International Journal of Circuit Theory and Applications , vol.23 , pp. 269-283
    • Gielen, G.1
  • 7
    • 84883796417 scopus 로고
    • Cadence Design Systems Inc 555 River Oaks Parkway San Jose California 95134, Oct.
    • Cadence Design Systems, Inc, 555 River Oaks Parkway, San .Jose, California 95 134, "SKILL Reference Manual," Oct. 1991.
    • (1991) SKILL Reference Manual
  • 9
    • 0003212510 scopus 로고
    • Analog module generators for silicon compilation
    • May
    • J. Kuhn, "Analog Module Generators for Silicon Compilation," VLSI System Design, pp. 75-80, May 1987.
    • (1987) VLSI System Design , pp. 75-80
    • Kuhn, J.1
  • 10
    • 0028711779 scopus 로고
    • Using C to write portable CMOS VLSI module generators
    • A. Greiner, et al., "Using C to Write Portable CMOS VLSI Module Generators," EURO-DAC 1994, pp. 676-681, 1994.
    • (1994) EURO-DAC 1994 , pp. 676-681
    • Greiner, A.1
  • 11
    • 0029779086 scopus 로고    scopus 로고
    • A novel analog module generator environment
    • March
    • M. Wolf, et al., "A Novel Analog Module Generator Environment," Proc. The European Design & Test Conference, pp. 388.-392, March 1996.
    • (1996) Proc the European Design & Test Conference , pp. 388-392
    • Wolf, M.1
  • 12
    • 0030644786 scopus 로고    scopus 로고
    • Application independent module generation in analog layouts
    • March
    • M. Wolf, et al., "Application Independent Module Generation in Analog Layouts," Proc. The European Design & Test Conference, p. 624, March 1997.
    • (1997) Proc the European Design & Test Conference , pp. 624
    • Wolf, M.1
  • 13
    • 84893749867 scopus 로고    scopus 로고
    • Automatic topology optimization for analog module generators
    • Paris, March
    • M. Wolf, et al., "Automatic Topology Optimization for Analog Module Generators," Proc. Design, Automation and Test in Europe, pp. 961-962, Paris, March 1998.
    • (1998) Proc. Design, Automation and Test in Europe , pp. 961-962
    • Wolf, M.1
  • 14
    • 0032218628 scopus 로고    scopus 로고
    • A novel design assistant for analog circuits
    • Feb
    • M. Wolf, et al., "A Novel Design Assistant for Analog Circuits," Proc. ASP-DAC, pp. 495-500, Feb. 1998.
    • (1998) Proc. ASP-DAC , pp. 495-500
    • Wolf, M.1
  • 15
    • 0031623466 scopus 로고    scopus 로고
    • New description language and graphical user interface for module generation in analog layouts
    • June
    • M. Wolf, et al., "New Description Language and Graphical User Interface for Module Generation in Analog Layouts," Proc. ISCAS Vol. VI, pp. 290-293, June 1998.
    • (1998) Proc. ISCAS , vol.6 , pp. 290-293
    • Wolf, M.1
  • 16
    • 0022297556 scopus 로고
    • Numerical simulation of resistive interconnects for integrated circuits
    • Dec
    • A. J. Walton, et al., "Numerical Simulation of Resistive Interconnects for Integrated Circuits," IEEE J. Solid- State Circuits, Vol. SC-20, No. 6, pp. 1252-1258, Dec. 1985.
    • (1985) IEEE J. Solid- State Circuits , vol.SC-20 , Issue.6 , pp. 1252-1258
    • Walton, A.J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.