-
1
-
-
0029779086
-
A novel analog module generator environment
-
Paris, March
-
M. Wolf, U. Kleine and B.J Hosticka, "A Novel Analog Module Generator Environmcnl," Proc. ED&TC, Paris, pp. 388-392, March 1996.
-
(1996)
Proc. ED&TC
, pp. 388-392
-
-
Wolf, M.1
Kleine, U.2
Hosticka, B.J.3
-
2
-
-
0032629282
-
Reliability driven module generation foe analog layouts
-
Orlando, May
-
M. Wolf and U. Klcine, "Reliability Driven Module Generation foe Analog Layouts," ISCAS'99, Orlando, 412-415, May 1999.
-
(1999)
ISCAS'99
, pp. 412-415
-
-
Wolf, M.1
Klcine, U.2
-
3
-
-
0010568159
-
A new design rule dcscription for automated layout tools
-
Beirut, Dez
-
L. Zhang, U. Kleine, T. Rudolph und M. Wolf: A new Design Rule Dcscription for Automated Layout Tools. ICECS'2000, Bcirut, 988-992, Dez. 2000.
-
(2000)
ICECS'2000
, pp. 988-992
-
-
Zhang, L.1
Kleine, U.2
Rudolph, T.3
Wolf, M.4
-
4
-
-
0032218628
-
A novel design assistant cor analog module generators
-
Yokohama, Feb.
-
M. Wolf, U. Kleine, and F. Schafer, "A Novel Design Assistant Cor Analog Module Generators," ASP-DAC98, Yokohama, 495-500, Feb. 1998.
-
(1998)
ASP-DAC98
, pp. 495-500
-
-
Wolf, M.1
Kleine, U.2
Schafer, F.3
-
5
-
-
77956424868
-
ALI: A procedural language to describe VLSI layout
-
R.J. Lipton, S.C. Norlh, R. Scdgewick, J. Valdes, and G Vijayan, "ALL A Procedural Language IO Dcscrihe VLSl Layout," IEEE DAC82, 1982.
-
(1982)
IEEE DAC'82
-
-
Lipton, R.J.1
Norlh, S.C.2
Scdgewick, R.3
Valdes, J.4
Vijayan, G.5
-
6
-
-
0003212510
-
Analog module generators for silicon compilation
-
May
-
J. Kuhn, "Analog Module Generators for Silicon Compilation," VLSl Syslem Design, pp. 75-80, May 1987.
-
(1987)
VLSl Syslem Design
, pp. 75-80
-
-
Kuhn, J.1
-
7
-
-
0024647840
-
ILAC: An automated layout tool for analog CMOS circuits
-
April
-
J. Rijmenants, et al., ILAC: An Automated Layoul Tool for Analog CMOS Circuits," IEEE J. Solid-State Circuits, Vol. 24,No. 2.pp.417-425,April 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, Issue.2
, pp. 417-425
-
-
Rijmenants, J.1
-
8
-
-
0029342926
-
An analogue module generator for mixed Analoguc/Digital ASIC Design
-
July-Aug.
-
G. Gielen. et. al., "An Analogue Module Generator for Mixed Analoguc/Digital ASIC Design," International J. of Circuit Theory and Applications, Vol.23, pp. 269-283, July-Aug. 1995.
-
(1995)
International J. of Circuit Theory and Applications
, vol.23
, pp. 269-283
-
-
Gielen, G.1
-
9
-
-
77956439213
-
A genetic approach to analog module placement with simulated anncaling
-
L. Zhang and U. Kleine, "A Genetic Approach to Analog Module Placement with Simulated Anncaling, Proc. ISCAS 2002
-
(2002)
Proc. ISCAS
-
-
Zhang, L.1
Kleine, U.2
-
10
-
-
0021586347
-
Random error effect in matched MOS capacitors and current sources
-
Dec.
-
J.-B. Shyu, G.C. Temes, F. Krummennacher, "Random error effect in matched MOS capacitors and current sources " IEEE J .Solid-State Circuits, Vol. SC-19, No. 6, pp. 948-955, Dec. 1984
-
(1984)
IEEE J .Solid-Statc Circuits
, vol.SC-19.
, Issue.6
, pp. 948-955
-
-
Shyu, J.-B.1
Temes, G.C.2
Krummennacher, F.3
-
11
-
-
0022891057
-
Characterization and modeling of mismatch in MOS transistors for prceision analog design
-
Dec.
-
K.R. Lakshmikumar, R.A. Hadaway, and M.A. Copeland, " Characterization and Modcling of Mismatch in MOS Transistors for Prccisioii Analog Design," I. of Solid-StaleCircuts ,Vol. SC-21, No.6, pp. 1057-1086, Dec. 1986.
-
(1986)
J. of Solid-StaleCircuts
, vol.SC-21
, Issue.6
, pp. 1057-1086
-
-
Lakshmikumar, K.R.1
Hadaway, R.A.2
Copeland, M.A.3
-
12
-
-
0024754187
-
Matching properties of MOS transistors
-
Oct.
-
M.J.M. Pelgrom, A.C.J. Duinmaijer, A.P.G. Welbers, "Matching Properties of MOS Transistors," J. of Solid-Slate Circuits, Vol. SC-24, No. 5, pp. 1433-1440, Oct. 1989.
-
(1989)
J. of Solid- Slate Circuits
, vol.SC-24
, Issue.5
, pp. 1433-1440
-
-
Pelgrom, M.J.M.1
Duinmaijer, A.C.G.2
Welbers, A.P.G.3
-
13
-
-
0029229608
-
Mismatch characterization of small size MOS transistors
-
March
-
J. Bastos, M. Sleyaert, R. Roovers, P. Klinget, W. Sansen, B. Graindourze, A. Pergool, and E. Janssens, "Mismatch characterization of small size MOS transistors," Proc. IEEE 1995 Int. Confercnce on Microclectronic Test Structures, Vol.8, pp, 271-276, March 1995.
-
(1995)
Proc. IEEE 1995 Int. Confercnce on Microclectronic Test Structures
, vol.8
, pp. 271-276
-
-
Bastos, J.1
Steyaert, M.2
Roovers, R.3
Klinget, P.4
Sansen, W.5
Graindourze, B.6
Pergool, A.7
Janssens, E.8
-
14
-
-
0024055902
-
An engineering model for short-channel MOS devices
-
Aug. ISCAS 2002
-
K. Toh, P. Koh, and R. Meyer," An Engineering Model for Short-Chdnnel MOS Devices," IEEE J.of Solid-State Circuits, Vol. SC-23, no. 4, pp. 950-957, Aug. 1988. ISCAS 2002.
-
(1988)
IEEE J.Of Solid-State Circuits
, vol.SC-23
, Issue.4
, pp. 950-957
-
-
Toh, K.1
Koh, P.2
Meyer, R.3
-
15
-
-
77956431658
-
-
private communication
-
R. Thcwes, private communication
-
-
-
Thewes, R.1
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