Analog layout using ALAS!

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 2, 1996, Pages 271-274

  Bruce, J D ^a   Li, H W ^b   Dallabetta, M J ^c   Baker, R J ^d  

^a MICRON TECHNOLOGY INC   (United States)

^b UNIVERSITY OF IDAHO   (United States)

^c HEWLETT PACKARD COMPANY   (United States)

^d Department of Electrical Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SOFTWARE; LINEAR INTEGRATED CIRCUITS; NETWORK COMPONENTS; OPTIMIZATION; TRANSISTORS;

ANALOG LAYOUT ASSISTANT; CALTECH INTERMEDIATE FORMAT; INTERDIGITATED DEVICE PAIRS; PASSIVE COMPONENTS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030083066     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.488007     Document Type: Article

References (4)

1. J. Cohn, D. Garrod, R. Rutenbar, and L. Carley, "KOAN/ANAGRAM II: New tools for device-level analog placement and routing," IEEE J. Solid-State Circuits, vol. 26, no. 3, pp. 330-342, Mar. 1991.
2. B. Owen, "The intermediate layout language," Ref. Doc., Univ. of Toronto, Nov. 1994.
3. U. Gatti, F. Maloberti, and V. Liberali, "Full stacked layout of analogue cells," in Proc. IEEE Int. Symp. on Circuits and Systems, May 1989, pp. 1123-1126.
4. M. Ismail and T. Fiez, Analog VLSI: Signal and Information Processing. New York, McGraw-Hill, ch. 15, 16, 1994.