FLAG: A flexible layout generator for analog MOS transistors

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 6, 1998, Pages 896-902

  Mathias, Herve ^b,c,d   Berger Toussan, Josette ^b,d   Jacquemod, Gilles ^a,b,e,f   Gaffiot, Frederic ^a,b   Le Helley, Michel ^a,b  

^a IEEE

^b ECOLE CENTRALE DE LYON   (France)

^c INSTITUT JEAN LAMOUR   (France)

^d GRENOBLE INSTITUTE OF TECHNOLOGY   (France)

^e CPE LYON   (France)

^f NSA Lyon   (France)

Author keywords

CMOS analog integrated circuits; Design automation; Layout; Operational amplifiers

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; LINEAR INTEGRATED CIRCUITS; MOSFET DEVICES; OPERATIONAL AMPLIFIERS;

CMOS ANALOG INTEGRATED CIRCUITS; FLEXIBLE LAYOUT GENERATOR;

INTEGRATED CIRCUIT LAYOUT;

EID: 0032099139     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.678653     Document Type: Article

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