A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs

IEEE Transactions on Nuclear Science

Volumn 52, Issue 6, 2005, Pages 2217-2223

  Sterpone, L ^a   Violante, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

Dependability evaluation; FPGA; Single event effects

Indexed keywords

FAILURE ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS; HARDENING;

CONFIGURATION MEMORY; DEPENDABILITY EVALUATION; SINGLE EVENT EFFECTS;

STATIC RANDOM ACCESS STORAGE;

EID: 33144481330     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2005.860745     Document Type: Conference Paper

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