On the evaluation of SEU sensitiveness in SRAM-based FPGAs

Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004

Volumn , Issue , 2004, Pages 115-120

  Bernardi, P ^a   Sonza Reorda, M ^a   Sterpone, L ^a   Violante, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

SEQUENTIAL LOGIC; SINGLE EVENT FUNCTIONAL INTERRUPT (SEFI); SINGLE EVENT UPSETS (SEU); TRIPLE MODULAR REDUNDANCY (TMR);

ENERGY UTILIZATION; FAULT TOLERANT COMPUTER SYSTEMS; FLIP FLOP CIRCUITS; LOGIC GATES; PROBABILITY; PROBLEM SOLVING; RANDOM ACCESS STORAGE; REDUNDANCY; SEQUENTIAL CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 10444269368     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2004.1319668     Document Type: Conference Paper

References (12)

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12. "Spartan-II 2.5V FPGA family: Introduction and Ordering Information", Xilinx Product Specification Datasheets, 2003