Designing fault-tolerant techniques for SRAM-based FPGAs

IEEE Design and Test of Computers

Volumn 21, Issue 6, 2004, Pages 552-562

  de Lima Kastensmidt, Fernanda Gusmão ^a   Neuberger, Gustavo ^b   Hentschke, Renato Fernandes ^b   Carro, Luigi ^b   Reis, Ricardo ^b  

^a UNIVERSIDADE ESTADUAL DO RIO GRANDE DO SUL   (Brazil)

^b FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MAJORITY LOGIC; REDUNDANCY; STATIC RANDOM ACCESS STORAGE;

CONCURRENT ERROR DETECTION; DUPLICATION WITH COMPARISON; TRIPLE MODULAR REDUNDANCY;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 11244318364     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2004.85     Document Type: Article

References (12)

1. A.H. Johnston, "Scaling and Technology Issues for Soft Error Rates," Proc. 4th Ann. Research Conf. Reliability, Stanford Univ., 2000; http://parts.jpl.nasa.gov/docs/Scal-00.pdf.
2. "Virtex 2.5 V Field Programmable Gate Arrays," DS003, v2.5, Product Specification, 2 Apr. 2001, Xilinx; http://direct.xilinx.com/ bvdocs/publications/ds003.pdf.
3. J. Barth, C. Dyer, and E. Stassinopoulos, "Space, Atmospheric, and Terrestrial Radiation Environments," IEEE Trans. Nuclear Science, vol. 50, no. 3, June 2003, pp. 466-482.
4. E. Normand, "Single Event Upset at Ground Level," IEEE Trans. Nuclear Science, vol. 43, no. 6, Dec. 1996, pp. 2742-2750.
5. D. Alexandrescu, L. Anghel, and M. Nicolaidis, "New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs," Proc. IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems, IEEE CS Press, 2002, pp. 99-107.
6. M. Rebaudengo, M.S. Reorda, and M. Violante, "Simulation-Based Analysis of SEU Effects of SRAM-Based FPGAs," Proc. Int'l Workshop Field-Programmable Logic and Applications, IEEE CS Press, 2002, pp. 607-615.
7. E. Fuller, M. Caffrey, and P. Blain, "Radiation Test Results of the Virtex FPGA and ZBT SRAM for Space Based Reconfigurable Computing," Proc. Int'l Conf. Military and Aerospace Applications of Programmable Logic Devices (MAPLD 02), NASA Office of Logic Design, 2002, pp. 1-8.
8. M. Ohlsson et al., "Neutron Single Event Upsets in SRAM-Based FPGAs," Proc. IEEE Nuclear Space Radiation Effects Conf. (NSREC 98), IEEE Press. 1998, pp. 1-4; http://www.xilinx.com/appnotes /FPGA_NSREC98.pdf.
9. C. Carmichael, "Triple Module Redundancy Design Techniques for Virtex Series FPGA," Xilinx Application Notes 197, v1.0, Mar. 2001, p. 137; http://www.xilinx.com/bvdocs/appnotes/xapp197.pdf.
10. F. Lima et al., "A Fault Injection Analysis of Virtex FPGA TMR Design Methodology," Proc. European Conf. Radiation and Its Effects on Components and Systems (RADECS 01), IEEE CS Press, 2001, pp. 275-282.
11. M. Lubaszewski and B. Courtois, "A Reliable Fail-Safe System," IEEE Trans. Computers, vol. 47, no. 2, Feb. 1998, pp. 236-241.
12. J. Patel and L. Fung, "Multiplier and Divider Arrays with Concurrent Error Detection," Proc. Int'l Symp. Fault-Tolerant Computing, IEEE CS Press, 1982, pp. 325-329.